View VITESSESEMICONDUCTORCORP-VSC8244XHG_7490391.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

vsc8244 data sheet quad 10/100/1000base-t phy with rgmii and rtbi mac interfaces vmds-10108 revision 4.1 june 2006 ? vitesse semiconductor corporation ? 741 calle plano ? camarillo, ca 93012 tel: (800) vitesse ? fax: (805) 987-5896 ? e-mail: prodinfo@vitesse.com internet: www.vitesse.com 1 of 121 1 general description ideally suited for high port density gigabit ethernet switches and routers, or multi-port ne twork interface cards (nics), vitesse's vsc8244 integrates four low-power, triple speed (10base-t, 100base-tx, a nd 1000base-t) ethernet transceivers in thermally-enhanced, 260-pin plastic ball grid array (bga). the vsc8244 physical layer "phy" ic leverages vitesse?s proprietary 4th generation dsp technology. vitesse's highly optimized dsp architecture yields industry leading performance at less than 640mw per port, supporting 1000base-t with respect to a ll worst case impairments (next, fext, echo, and s ystem noise sources). each of the four independen t triple-speed transceivers features pin-efficient rgmii and rtbi compliant mac interfaces. on-chip rgmii/rtbi series termination resistors simplify board design challenges by improving signal integrity and completely eliminating dozens of external series termination resistors on the receive side of the mac interface. in addition, the vsc8244 integrates, for the first time in the industry, all copper media side line termination resistors. to enable maximum network management feedback to the host system and the user, the veriphy ? link management and cable diagnostics suite can be used with the device. veriphy provides extensive network and cable plant operating and status information, such as the cable length, termination status, and open/short fault location. veriphy integrates with nic or switch software to greatly simplify gigabit ethernet network deployment and management by providing the functionality equivalent to a hand-held cable tester. 2 system diagrams figure 1. vsc8244 system diagram management i/f 1.2 v mdc, mdio mdint#_n serial i/f vsc8244 quad 10/100/1000base-t transceiver 3.3 v optional eeprom rgmii, rtbi 10/100/1000 mbps ethernet mac 10/100/1000 mbps ethernet mac 10/100/1000 mbps ethernet mac 10/100/1000 mbps ethernet mac rj-45 simpliphy?d magnetics rj-45 simpliphy?d magnetics rj-45 simpliphy?d magnetics rj-45 simpliphy?d magnetics
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 2 of 121 4 applications 3 features benefits ? quad, low power, 10/100/1000base-t in a 19mm hs-bga package ? catalyzes market for low-co st & high density lan, wan, san, & man switches ? lowest power consumption in the industry at less than 640mw/port (10 00base-t mode) ? eliminates heatsinks and fans for gigabit to the desktop lan switches ? supports picmg 2.16 and 3.0 ethernet backplanes at less than 500 mw/port ? lowest power mode reduces supply costs ? patented, low emi line driver with integrated line side termination resistors ? removes 12 passive components per phy*, reducing pcb area & cost by 50% ? saves up to 50% on magnetic module cost with simpliphy?d magnetics ? enables magnetic-less picmg backplane designs ? supports rgmii v1.3 (2.5v & 3.3v) & v2.0 (1.5v hstl) ? co mpatible with a wide variety of parallel i/f switch ics ? user-programmable rgmii timing compensation ? simplifies pcb layout; eliminates pcb trombones ? compliant with ieee 802.3 (10base-t, 100base-tx, 1000base-t) specifications ? ensures seamless deployment throughout copper networks with industry?s highest tolerance to noise and substandard cable plants ? >10kb jumbo frame support with programmable synchronization fifos ? provides for maximum jumb o frame sizes in custom san and lan systems ? five direct drive leds per port with on-chip filtering or serial led interface option ? eliminates external components and emi issues ? three user configuration options: 1) optional serial eeprom, 2) hardware configur ation pins, or 3) serial management interface (smi) ? offers design engineer a solution to fit any unmanaged or managed system requirement ? full suite of bist, near-end, and far-end loopback modes ? simplifies comprehensive in -system test to ensure highest product quality ? veriphy ? cable diagnostics ? pin-points potential cable pl ant problems by providing equivalent diagnostic capab ilities of a sophisticated hand-held cable tester ? automatic detection and correction of cable pair swaps, pair skew and pair polarity, along with hp auto mdi/ mdi-x crossover function ? compatible with 1st gen eration 1000base-t phys. ? supports auto mdi/mdi-x even when autonegotiation is disabled ? manufactured in advanced 0.13 m, 3.3v/1.2v digital cmos process ? most cost effective technology eliminates more expensive analog process variants * or, 576 components for a 48-port switch ? high port density 10/1 00/1000base-t switches ? gigab it ethernet-based san, nas, and man systems ? workgroup lan switches & routers ? high perfo rmance workstations & multi-port server nics ? backplane applications such as picmg 2.16, 3.0
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 3 of 121 5 device block diagram figure 2. vsc8244 block diagram 1 1 n = port number (0, 1, 2, 3) control led interface pcs decoder pcs encoder timing recovery + dac hybrid vga adc ffe pma (dsp data pump) pcs mdi (analog front end) 4 tx fir x4 nc1 nc2 nc3 ec led[4:0]_n clk125 mac ref_filt xtal1/2 ref_rext txd[3:0]_n tx_ctl_n tx_clk_n rxd[3:0]_n mac i/f port 3 port 2 port 1 trellis decoder pam-5 symbol mapper, scrambler pam-5 symbol de-mapper, descrambler port 0 rx_ctl_n rx_clk_n rgmii or rtbi interface selection and autonegotiation txvp_a_n txvn_a_n txvp_b_n txvn_b_n txvp_c_n txvn_c_n txvp_d_n txvn_d_n system jtag test manager management interface tdi trst tms tck tdo cmode[7:0] reset eeclk eedat mdint_n mdio mdc soft_reset clk125 micro
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 4 of 121 contents 1 general description ........................................................................................................... .............................. 1 2 system diagrams ............................................................................................................... .............................. 1 3 features benefits............................................................................................................. ................................. 2 4 applications .................................................................................................................. .................................... 2 5 device block diagram.......................................................................................................... ............................ 3 6 relevant specifications & documentation............ ........................................................................... ............ 12 7 vsc8244 differences vs. vsc8224/vsc8234 devices ... ............................................................................ .13 7.1 vsc8244 functional differences ............................................................................................. .................................13 7.2 vsc8244 register differences .......................... ..................................................................... ..................................13 7.3 vsc8244 pinout differences ................................................................................................. ...................................14 8 data sheet conventions ........................................................................................................ ........................ 14 9 package pin assignments & signal descriptions................................................................................. ...... 15 9.1 260 hs-pbga package ball diagram ..................... ...................................................................... ...........................15 9.2 bga ball to signal name cross reference (left side ) ....................................................................... ..................16 9.3 bga ball to signal name cross reference (right side) ................... .................................................... .................17 9.4 signal type descriptions ................................................................................................... .......................................18 9.5 mac transmit interface (mac tx) pins ............... ........................................................................ ............................19 9.6 mac receive interface (mac rx) pins ................ ........................................................................ ............................20 9.7 twisted pair interface pins ........................ ........................................................................ .......................................21 9.8 serial management interface pins (ieee smi) ........ .............. .............. ........... ........... ........... ........... .........................22 9.9 serial eeprom interface pins . .............. .............. .............. .............. .............. .............. .......... ..................................23 9.10 configuration and control pins ..................... ....................................................................... .....................................23 9.11 system clock interface pins ............................................................................................... ......................................24 9.12 led interface pins ........................................................................................................ ............................................24 9.13 jtag test access port pins ................................................................................................ .....................................25 9.14 analog bias pins .......................................................................................................... .............................................25 9.15 hstl voltage reference pins ................................................................................................ .................................. 25 9.16 no connect pins ............................................................................................................ .......................................... 26 9.17 power supply pins ......................................................................................................... ...........................................26 9.18 power supply and associated functional pins ..... .............. .............. .............. ........... ........... .......... ..........................27 10 system schematics............................................................................................................ ............................ 28 10.1 input clock options ....................................................................................................... ...........................................29 10.2 analog bias pins configuration ............................................................................................ ....................................30 11 mac interfaces ............................................................................................................... ................................ 31 11.1 rgmii mac i/f ............................................................................................................. ............................................31 11.2 rtbi mac i/f .............................................................................................................. ..............................................32
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 5 of 121 12 twisted pair interfac e....................................................................................................... .............................. 33 12.1 twisted pair auto negotiation (ieee802.3 clause 28) ...... .............. .............. .............. .............. .......... .......................33 12.2 twisted pair auto mdi/mdi-x function ............. ......................................................................... ..............................34 12.3 auto mdi/mdi-x in forced 10/100 link speeds ............................................................................... ........................34 12.4 twisted pair link speed downshif t ............... .............. .............. .............. ........... ........... .......... ..................................34 13 transformerless ethernet operati on for picmg 2.16 and 3.0 ip-based backplanes ............................... 35 14 serial management interface (smi) ............................................................................................ ................... 35 14.1 smi interrupt ............................................................................................................. ................................................36 15 parallel led interface.................................. ..................................................................... .............................. 38 16 serial led output............................................................................................................ ............................... 41 17 test mode interface (jtag) ................................................................................................... ........................ 42 17.1 supported instructions and instruction codes .............................................................................. ............................43 17.2 boundary-scan register cell order ......................................................................................... ................................44 18 veriphy cable diagnostics .... ................ ................ ................. ................ ................ ............... ....................... 45 18.1 coupling between cable pairs .... .............. .............. .............. .............. .............. ........... ......... ...................................45 18.2 cable pair termination .................................................................................................... .........................................45 18.3 cable length .............................................................................................................. ..............................................45 18.4 using veriphy in normal operating mode ............ .............. .............. ........... ........... ............ .......... ............................45 19 actiphy power management..................................................................................................... .................... 46 19.1 operation in actiphy mode ...... .............. .............. .............. .............. .............. ........... .......... .....................................46 19.2 low power state ........................................................................................................... .............................................47 19.3 lp wake up state .......................................................................................................... ............................................47 19.4 normal operating state .................................................................................................... ..........................................47 20 ethernet in-line powered device support ...................................................................................... .............. 48 20.1 cisco in-line powered device de tection .................................................................................... ..............................48 20.2 in-line power ethernet switch diagram ..................................................................................... ..............................48 20.3 in-line powered device detection (cisco method) . .......................................................................... .......................49 20.4 ieee 802.3af (dte power via mdi) .............. .............. .............. .............. .............. ........... ......... ................................49 21 advanced test modes .......................................................................................................... .......................... 49 21.1 ethernet packet generator (epg) ........................................................................................... .................................49 21.2 crc counter ........ .............. .............. .............. .............. .............. ............ ........... .......... .............................................49 21.3 far-end loopback .......................................................................................................... ...........................................50 21.4 near-end loopback ......................................................................................................... .........................................50 21.5 connector loopback ........................................................................................................ .........................................51 22 initialization & configuration. .............................................................................................. .......................... 52 22.1 resets .................................................................................................................... ...................................................52 22.2 power-up sequence ...... .............. .............. .............. .............. ........... ........... ........... .......... ........................................52 22.3 cmode pin configuration ................................................................................................... .....................................52 22.4 eeprom interface ..... .............. .............. .............. .............. ........... ........... ............ ........... .........................................55
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 6 of 121 23 mii register set............................................................................................................. .................................. 61 23.1 mii extended page registers ... .............. .............. .............. .............. .............. ........... ........... ....................................62 23.3 mii register quick reference ............................................................................................ .....................................63 23.4 mii register quick reference - extended page mode ....... .............. .............. .............. .............. .......... ....................65 24 mii register descriptions .................................................................................................... .......................... 66 24.1 register 0 (00h) ? mode control register ......... ......................................................................... ..............................66 24.2 register 1 (01h) ? mode status register ........... ........................................................................ ...............................67 24.3 register 2 (02h) ? phy identifier register #1 .... .............. .............. ........... ............ ........... ........... ..............................67 24.4 register 3 (03h) ? phy identifier register #2 .... .............. .............. ........... ............ ........... ........... ..............................67 24.5 register 4 (04h) ? auto-negotiation advertisement r egister ................................................................ ...................68 24.6 register 5 (05h) ? auto-negotiation link partner abil ity register ......................................................... ...................68 24.7 register 6 (06h) ? auto-negotiation expansion regi ster .................................................................... .....................68 24.8 register 7 (07h) ? auto-negotiation next-page transmi t register ........................................................... ...............69 24.9 register 8 (08h) ? auto-negotiation link partner next -page receive register ........ .............. .............. ........... ........69 24.10 register 9 (09h) ? 1000base-t cont rol register .............. .............. .............. ........... ........... ........... .........................70 24.11 register 10 (0ah) ? 1000base-t st atus register .. .............. .............. ........... ........... ........... ............ ........................72 24.12 register 11 (0bh) ? reserved register .................................................................................... ................................72 24.13 register 12 (0ch) ? reserved re gister .................................................................................... ................................72 24.14 register 13 (0dh) ? reserved re gister .................................................................................... ................................72 24.15 register 14 (0eh) ? reserved register ............. ....................................................................... ................................73 24.16 register 15 (0fh) ? 1000base-t stat us extension register #1 ............ .............. .............. ........... ........... ................73 24.17 register 16 (10h) ? 100base-tx stat us extension register .............. .............. .............. .............. ......... ..................74 24.18 register 17 (11h) ? 1000base-t status extension r egister #2 .............................................................. ................74 24.19 register 18 (12h) ? bypass control register .............................................................................. .............................75 24.20 register 19 (13h) ? reserved.............................................................................................. ..................................... 77 24.21 register 20 (14h) ? reserved ....................... ...................................................................... ......................................77 24.22 register 21 (15h) ? reserved ....................... ...................................................................... ......................................77 24.23 register 22 (16h) ? extended control & status regi ster .......... .............. ........... ........... ........... .......... .......................78 24.24 register 23 (17h) ? extended phy control register #1 ............. .............. .............. .............. .............. ......................79 24.25 register 24 (18h) ? extended phy control register #2 ............. .............. .............. .............. .............. ......................81 24.26 register 25 (19h) ? interrupt mask register ... ........................................................................... ...............................83 24.27 register 26 (1ah) ? interrupt status register . ........................................................................... ...............................84 24.28 register 27 (1bh) ? led control register ................................................................................. ...............................86 24.29 register 28 (1ch) ? auxiliary control & status re gister ........ .............. ........... ........... ........... ........... .........................87 24.30 register 29 (1dh) ? reserved ........................ ..................................................................... .....................................89 24.31 register 30 (1eh) - reserved ............................................................................................. ......................................89 24.32 register 31 (1fh) ? extended page access ......... .............. .............. ........... ........... ............ .......... ............................89 24.33 register 16e (10h) - reserved ..................... ....................................................................... .....................................90 24.34 register 17e (11h) - clk125micro clock enable . ........................................................................... .........................90 24.35 register 18e (12h) - reserved ..................... ....................................................................... .....................................90 24.36 register 19e (13h) - reserved ..................... ....................................................................... .....................................90 24.37 register 20e (14h) - extended phy control register #3 ........... .............. .............. .............. ............... .....................91 24.38 register 21e (15h) - eeprom interf ace status and control r egister ........... ........... ........... ............ ........... .............92
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 7 of 121 24.39 register 22e (16h) - eeprom data read/write regi ster ....... .............. .............. .............. ........... ......... ..................93 24.40 register 23e (17h) - extended phy control register #4 ........... .............. .............. .............. ............... .....................93 24.41 register 24e (18h) ? reserved ...................... ...................................................................... ....................................94 24.42 register 25e (19h) ? reserved ...................... ...................................................................... ....................................94 24.43 register 26e (1ah) ? reserved ............................................................................................ ....................................94 24.44 register 27e (1bh) ? reserved ............................................................................................ ....................................94 24.45 register 28e (1ch) ? reserved ............................................................................................. ................................... 94 24.46 register 29e (1dh) - 1000base-t ethe rnet packet generator (epg) register #1............ .............. ........... .......... .. 95 25 electrical specifications .................................................................................................... ............................ 96 25.1 absolute maximum ratings ......... ......................................................................................... ....................................96 25.2 recommended operating conditions ............. .............. .............. .............. .............. ............ ......... .............................97 25.3 thermal application data .................................................................................................. ........................................98 25.4 package thermal specifications - 260 hs-pbga ............................................................................. ......................98 25.5 current and power consumption es timates ................................................................................... ..........................99 25.6 dc specifications ......................................................................................................... ...........................................100 25.7 clocking specifications ................................................................................................... ........................................102 25.8 system timing specifications .............................................................................................. ...................................103 26 packaging specifications ..................................................................................................... ........................115 26.1 19mm hs-pbga mechanical specification ..................................................................................... ....................... 115 26.2 package moisture sensitivity ........................ ...................................................................... .................................... 115 27 ordering information......................................................................................................... ............................116 27.1 devices ................................................................................................................... ................................................ 116 27.2 related devices ........................................................................................................... ........................................... 116 28 design guidelines ....................................... ..................................................................... .............................117 28.1 required smi register write sequence ...................................................................................... ........................... 117 28.2 interoperability with intel 82547e1 l322sq96 ........... .............. .............. .............. .............. ........... ......................... 117 29 product support ......... ................ ................. ................ ................ ............. ............. .......... ..............................119 29.1 available documents and application notes ........... .............. .............. .............. .............. .............. ......................... 119 30 document history & notices ................................................................................................... .................... 120
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 8 of 121 figures figure 1. vsc8244 system diagram ............................................................................................... ...................................1 figure 2. vsc8244 block diagram ................................................................................................ .....................................3 figure 3. 260 hs-pbga package ball diagram ................. .................................................................... ..........................15 figure 4. 260-pin hs-pbga (19mm) signal map (top left si de of package) ......................................................... .....16 figure 5. 260-pin hs-pbga (19mm) signal map (top right side of package) ........................................................ ....17 figure 6. general system schematic (shown with rgmii and 3.3v i/o) ............................................................. ............28 figure 7. crystal clock option ................................................................................................. .........................................29 figure 8. 25 mhz reference clock option ................... ...................................................................... ..............................29 figure 9. 125 mhz reference clock opti on ........................................................................................ .............................30 figure 10. analog bias pins ground connection diagram .......................................................................... .......................30 figure 11. rgmii mac interface ................................................................................................. .......................................31 figure 12. rtbi mac interface .................................................................................................. .........................................32 figure 13. twisted pair interface .............................................................................................. ..........................................33 figure 14. mdio read frame ..................................................................................................... .......................................36 figure 15. mdio write frame .................................................................................................... .........................................36 figure 16. logical representation of op en-drain (active-low) mdint_n pin ....................................................... ............37 figure 17. logical representation of op en-source (active-high) mdint_n pin ..................................................... ..........37 figure 18. test access port and boundary scan architectu re ..................................................................... ......................42 figure 19. actiphy state diagram ............................................................................................... .......................................46 figure 20. in-line powered ethernet switch diagram ..... ........................................................................ ............................48 figure 21. far-end loopback block diagram ...................................................................................... ...............................50 figure 22. near-end loopback block diagram ..................................................................................... ..............................50 figure 23. connector loopback .................................................................................................. .......................................51 figure 24. vsc8244 devices connected to use the same star tup eeprom ........................................................... ........57 figure 25. eeprom read and write register flow ... .............. .............. .............. .............. ........... ........... .........................60 figure 26. extended page register . .............. .............. .............. .............. .............. ........... ............ ......................................62 figure 27. rgmii uncompensated ac timing and multiplexing ...................................................................... ................104 figure 28. rgmii compensated ac timing and multiplexing .............. .............. ............ ........... ........... .......... ..................105 figure 29. rtbi uncompensated ac timing and multiplexing ............. .............. ............ ........... ........... .......... ..................107 figure 30. rtbi compensated ac timing and multiplexing ......................................................................... ....................108 figure 31. jtag interface ac timing ............................................................................................ ...................................109 figure 32. smi ac timing ....................................................................................................... .......................................... 110 figure 33. led_clk and led_data output ac timing ............................................................................... .................. 111 figure 34. refclk ac timing .................................................................................................... ..................................... 112
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 9 of 121 figure 35. clk125 ac timing .................................................................................................... ...................................... 113 figure 36. reset ac timing .. .............. .............. .............. .............. ........... ........... ........... .......... ...................................... 114 figure 37. 19mm hs-pbga mechanical specification ............................................................................... ...................... 115
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 10 of 121 tables table 1. vsc8244 relevant specifications ........................................................................................ ............................. 12 table 2. vsc8224/vsc8234/vsc8244 mac / media interface s upport options........ .............. .............. ........... ........... . 13 table 3. data sheet conventions................................................................................................. ................................... 14 table 4. signal type descriptions ............................................................................................... .................................... 18 table 5. mac tx signal descriptions . .............. .............. .............. .............. .............. ........... ........... ................................ 19 table 6. mac rx signal descriptions ............................................................................................. ................................ 20 table 7. twisted pair interface pins ..................... ....................................................................... .................................... 21 table 8. serial management interface pins .............. ......................................................................... ............................. 22 table 9. serial eeprom interface pins ............... .............. .............. .............. .............. ........... ......... ............................... 23 table 10. configuration and control pins........................................................................................ .................................. 23 table 11. system clock interface pins........................................................................................... ................................... 24 table 12. led interface pins.................................................................................................... ......................................... 24 table 13. jtag tap signal descriptions .......................................................................................... ................................ 25 table 14. analog bias pins ...................................................................................................... ......................................... 25 table 15. hstl voltage reference pins ..................... ...................................................................... ................................ 25 table 16. no connect pins....................................................................................................... ......................................... 26 table 17. power supply pins ..................................................................................................... ....................................... 26 table 18. power supply and associated functional pins . .............. .............. .............. ........... ........... .......... ...................... 27 table 19. accepted mdi pair connection combinations...... .............. .............. ........... ........... ........... .......... ...................... 34 table 20. smi frame format ...................................................................................................... ...................................... 35 table 21. led function assignments ......................... ..................................................................... ................................. 38 table 22. led functions ......................................................................................................... .......................................... 38 table 23. led output options .................................................................................................... ...................................... 40 table 24. serial led output data .......................... ...................................................................... ..................................... 41 table 25. jtag device identification register descripti on ....................................................................... ........................ 43 table 26. jtag interface instructio n codes................ .............. .............. .............. .............. .............. ................................ 43 table 27. cmode hardware configuration bits ............ ......................................................................... .......................... 53 table 28. cmode pin combinations ................................................................................................ ................................ 53 table 29. cmode configuration bits .............................................................................................. .................................. 54 table 30. eeprom configurat ion contents ............ .............. .............. .............. .............. ............ ......... ............................ 55 table 31. eeprom configuration contents for multiple vsc 8244 devices......... .............. .............. ............ ........... ......... 57 table 32. mii register bit modes ........................... ..................................................................... ...................................... 61 table 33. mii register quick reference .................. ........................................................................ ................................. 63 table 34. mii register quick reference - extended page mode............ .............. ........... ............ ........... ......... ................. 65
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 11 of 121 table 35. transmitter/receiver test mode............... ......................................................................... ................................ 70 table 36. test mode 4 ........................................................................................................... ............................................ 71 table 37. transmitter test clock enable......................................................................................... .................................. 76 table 38. mac/media interface mode select ....................................................................................... ............................. 80 table 39. thermal air flow specifications - 260 ball hsbg a 19mm package......................................................... ......... 98 table 40. thermal specifications - 260 ball hsbga 19mm pa ckage.................................................................. .............. 98 table 41. current and power consumption estimates - hstl @ 1.5v, rgmii mode, no leds, no clk125 .................. 99 table 42. current and power consumption estimates - 2.5v, rg mii mode, no leds, no clk125 ................................. 99 table 43. current and power consumption estimates - 3.3v, rg mii mode, no leds, no clk125 ................................. 99 table 44. digital pins specifications (vddio = 3.3v) ............................................................................ ......................... 100 table 45. digital pins specifications (vddio = 2.5v) ............................................................................ ......................... 100 table 46. digital pins specifications (vddio = 1.5v) ............................................................................ ......................... 101 table 47. led output pins specifications........................................................................................ ............................... 102 table 48. reference clock option specifications ....... .......................................................................... .......................... 102 table 49. crystal option specifications .................. ....................................................................... .................................. 103 table 50. rgmii mode ac timing specifications........... ........................................................................ ......................... 103 table 51. rtbi mode ac timing specifications .......... .......................................................................... .......................... 106 table 52. jtag interface ac timing specifications ............................................................................... ......................... 109 table 53. smi ac timing specifications.......................................................................................... ................................ 110 table 54. mdint ac timing specifications........................................................................................ ............................. 111 table 55. led_clk and led_data output ac timing specif ication ................................................................... ......... 111 table 56. refclk ac timing specifications.............. ......................................................................... ........................... 112 table 57. clk125 ac timing specifications ....................................................................................... ............................ 113 table 58. reset ac timing specificat ion............. .............. .............. .............. .............. ........... ......... ............................. 114 table 59. startup write sequence changes ........................................................................................ ........................... 117 table 60. startup write sequence changes for intel 82547e1 interoperability ..................................................... ......... 118 table 61. document revision history ......................... .................................................................... ................................ 120
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 12 of 121 6 relevant specificat ions & documentation the vsc8244 conforms to the following specifications. pl ease refer to these documents for additional information. table 1. vsc8244 relevant specifications specification - revision description ieee 802.3-2002 carrier sense multiple access with collis ion detection (csma/cd) access method and physical layer specifications . ieee 802.3-2002 cons olidates and superse des the following specifications: 802.3ab (1000base-t), 802 .3u (fast ethernet), with references to ansi x3t12 tp-pmd standard ( ansi x3.263 tp-pmd ). ieee 1149.1-1990 test access port and boundary scan architecture 1 . includes ieee standard 1149.1a-1993 and ieee standard 1149.1b-1994. 1 often referred to as the ?jtag? test standard. jedec eia/jesd8-5 2.5v0.2v (normal range), and 1.8v to 2.7v (wide range) power supply voltage and interface standard for nonterminated digital integrated circuits. jedec jesd22-a114-b electrostatic discharge (esd) sensitivity testing human body model (hbm). revision of jesd22-a114-a. jedec jesd22-a115-a electrostatic discharge (esd) sensitivity testing machine model (mm). revision of eia/jesd22-a115. jedec eia/jesd78 ic latch-up test standard. mil-std-883e miltary test method standard for microcircuits. rgmii specification - v1.3, v2.0 reduced pin-count interface for gigabit et hernet physical layer devices (per hewlett packard). includes both rgmii and rtbi standards. picmg 2.16 ip backplane specification for compactpci v2.16. advanced tca? base picmg 3.0 ip backplane specification for compactpci v3.0. cisco inline power detection algorithmn cisco sytems inline power detection: http://www.cisco.com/en/us /products/hw/phones/ps379/ products_tech_note09186a00801189b5.shtml
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 13 of 121 7 vsc8244 differences vs . vsc8224/vsc 8234 devices the vsc8244 is one of three, quad port phy devices featuri ng vitesse?s proprietary fourth-generation dsp technology. it provides parallel rgmii/rtbi interfaces and 10/100/1000base-t category-5, unshiel ded twisted pair (utp) copper media interfaces. the vsc8234 features serial sgmii/serdes mac interfaces with cate gory-5 utp media interfaces. the vsc8224 is the dual media capable device featuring rgmii/rtbi parallel mac interfaces wi th support for both 10/100/1000base-t and 1000base-x media interfaces. the following table summarizes the mac and media interfac es supported by the vsc8244, the vsc8234, and the vsc8244 quad-port phy: 7.1 vsc8244 functional differences the vsc8244 is a functional subset of the vsc8224 in that it provides all the same features except for the following: ? no media side serdes interfaces for supporting 1000base-x (fiber). ? differences in the cmode configurations settings as certain functions in the vsc8224 relating to the serial interface are not present in the vs c8244. this includes several mac interfaces, sigdet direction setting, and serdes termination impedance setting 7.2 vsc8244 register differences the vsc8244 is the exact register map equivalent to th e vsc8224?s register map with the following exceptions: ? register 3: device number indication changes to vsc8244. ? register 23: ? bit 15 is reserved and must be set to 0. ? bits 14:12 less modes are present. only modes involving rgmii-cat5 and rtbi-cat5 exist in the vsc8244. ? register 24: txfifo settings only affect rgm ii as opposed to serdes and sgmii as in the vsc8224. ? register 25 & 26: bit 4 for the auto-media sense (ams) indication condition is not available. ? register 16e: only bits 2:0 (remote faul t bit settings) are relevant on the vsc8244. ? register 20e: bits 7:5 related to ams and serdes termination impedance for the vsc8224 are not present in the vsc8224. table 2. vsc8224/vsc8234/vsc8244 mac / media interface support options device # mac interface media interface package options full part number vsc8224 rgmii / rtbi cat-5 260-pin hs-pbga vsc8224hg rgmii / rtbi serdes (1000base-x) vsc8234 sgmii (4 or 6 pin) cat-5 260-pin hs-pbga vsc8234hg serdes (1000base-x) cat-5 vsc8244 rgmii / rtbi cat-5 260-pin hs-pbga vsc8244hg
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 14 of 121 7.3 vsc8244 pinout differences the 260-pin hs-pbga packages between t he vsc8224hg and the vsc8244hg are the exact same (pin-for-pin compatible), except for the following pins: the following pins are nc on the vsc8244hg 260-pin hs-pbga: ? pins t1, m1, h1, d1, u1, n1, j1, e1 -- tdp/n_[3:0] signals ? pins r1, l1, g1, c1, p1, k1, f1, b1 -- rdp/n_[3:0] signals ? pins r2, l2, g2, c2, t2, m2, h2, d2 -- rcp/n_[3:0] signals ? pins e2, j2, n2, u2 -- sigdet_[3:0] signals 8 data sheet conventions conventions used throughout this data sheet are specified in the following table. table 3. data sheet conventions convention syntax examples description register number registernumber.bit or registernumber.bitrange 23.10 23.12:10 register 23 (address 17h), bit 10. register 23 (address 17h), bits 12, 11, and 10. extended page regis- ter number registernumbere.bit or registernumbere.bitrange 23e.10 23e.12:10 extended register 23 (address 17h), bit 10. extended register 23 (address 17h), bits 12, 11, and 10. signal name (active high) signalname 1 1 all signal names are in all capital letters. pllmode signal name for pllmode. signal name (active low) signalname 1 reset active low reset signal. signal bus name busname[msb:lsb] 1 cmode[4:0] 2 2 cmode is common to entire device. cmode configuration bits 4, 3, 2, 1, and 0. phy port number _n _3 denotes a specific phy port #3. n= {3 || 2 || 1 ||0}. phy-specific port signal signalname_n 1 rx_ctl_3 rx_ctl signal for phy port 3 3 . 3 rxd signals are unique to each phy. signal bus for a specific phy port signalname[msb:lsb]_n 1 rxd[3:0]_3 receive data bus, bits 3through 0, for phy port #3 3 .
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 15 of 121 9 package pin assignments & signal descriptions 9.1 260 hs-pbga package ball diagram for complete specifications, refer to section 26: ?packaging specifications? . figure 3. 260 hs-pbga package ball diagram (view from top of package with underly ing bga ball positions superimposed) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 vsc8244 260 hs-pbga 1.0mm ball pitch (19mm body size) (top view) a b c d e f g h j k l m n p r t u v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 a b c d e f g h j k l m n p r t u v
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 16 of 121 9.2 bga ball to signal name cross reference (left side) figure 4. 260-pin hs-pbga (19mm) signal map (top left side of package) 1 2 3 4 5 6 7 8 9 a led[4]_3 led[0]_2 txvpd_3 txvpc_3 txvpb_3 txvpa_3 txvpd_2 txvpc_2 txvpb_2 b nc led[1]_2 txvnd_3 txvnc_3 txvnb_3 txvna_3 txvnd_2 txvnc_2 txvnb_2 c nc nc led[2]_2 led[3]_2 led[4]_2 nc nc vdd33 ref_rext d nc nc led[3]_3 vdd33 vdd33 vdd33 vsss vsss vdd33 e nc nc led[2]_3 vdd12 f nc vsss led[1]_3 vdd12 g nc nc led[0]_3 vsss vsss vsss vsss h nc nc vdd12 vdddig vsss vsss vsss j nc nc vdd12 vdddig vsss vsss vsss k nc vsss vsss vsss vsss vsss vsss l nc nc vsss vdd33 vsss vsss vsss m nc nc vdd12 vsss vssio vssio vssio n nc nc vdd12 vsss p nc vsss vsss vdddig r nc nc vdd12 vdddig vddio mac vddio mac vddio mac txref_2 vddio mac t nc nc txref_3 rxd[2]_3 tx_clk_3 txd[2]_3 rx_clk_2 rxd[2]_2 tx_clk_2 u nc nc rx_ctl_3 rxd[1]_3 tx_ctl_3 txd[1]_3 rx_ctl_2 rxd[1]_2 tx_ctl_2 v nc rx_clk_3 rxd[3]_3 rxd[0]_3 txd[3]_3 txd[0]_3 rxd[3]_2 rxd[0]_2 txd[3]_2 1 2 3 4 5 6 7 8 9
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 17 of 121 9.3 bga ball to signal name cross reference (right side) figure 5. 260-pin hs-pbga (19mm) sign al map (top right side of package) 10 11 12 13 14 15 16 17 18 txvpa_2 txvpd_1 txvpc_1 txvpb_1 txvpa_1 txvpd_0 txvpc_0 txvpb_0 txvpa_0 a txvna_2 txvnd_1 txvnc_1 txvnb_1 txvna_1 txvnd_0 txvnc_0 txvnb_0 txvna_0 b ref_filt vsss vsss vsss vsss nc cmode[7] cmode[6] cmode[5] c vdd33 vdd33 vdd33 vdd33 vdd12 vdd12 cmode[4] xtal1 or refclk xtal2 d nc cmode[3] cmode[2] cmode[1] e vdd33 cmode[0] led[0]_1 led[1]_1 f vsss vsss vsss vdd33 led[2]_1 led[3]_1 led[4]_1 g vsss vsss vsss vdddig led[0]_0 led[1]_0 led[2]_0 h vsss vsss vsss vdddig tdi led[3]_0 led[4]_0 j vsss vsss vsss vddio ctl tdo tck tms k vsss vsss vsss vddio micro trst eeclk or pllmode eedat l vssio vssio vssio vssio reset soft_ reset oscen or clk125 micro m vsss mdint_1 mdint_2 mdint_3 n vsss mdc mdio mdint_0 p txref_1 vddio mac vddio mac txref_0 vdddig vdddig vdd33 clk125 mac microref r txd[2]_2 rx_clk_1 rxd[0]_1 txd[3]_1 txd[0]_1 rxd[3]_0 rxd[0]_0 txd[3]_0 txd[0]_0 t txd[1]_2 rx_ctl_1 rxd[1]_1 tx_clk_1 txd[1]_1 rx_ctl_0 rxd[1]_0 tx_ctl_0 txd[1]_0 u txd[0]_2 rxd[3]_1 rxd[2]_1 tx_ctl_1 txd[2]_1 rx_clk_0 rxd[2]_0 tx_clk_0 txd[2]_0 v 10 11 12 13 14 15 16 17 18
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 18 of 121 9.4 signal type descriptions table 4. signal type descriptions symbol signal type description i digital input standard digital input signal. no internal pull-up or pull-down. i pu digital input with pull-up standard digital input. includes on-chip 100k pull-up to vddio. i pd digital input with pull-down standard digital input. includes on-chip 100k pull-down to vssio. o zc impedance controlled output 50 integrated (on-chip) source series te rminated, digital output signal. used pri- marily for timing-sensitive mac i/f and 125mhz clock output pins, in addition to high speed manufacturing test mode pins. i pd /o digital bidirectional tristate-able, digital input and output signal. includes on-chip 100k pull-down to vssio. od digital open drain output open drain digital output signal. must be pulled to vddio through an external pull- up resistor. a diff analog differential analog differential signal pair for twisted pair interface. a bias analog bias analog bias or reference signal. must be ti ed to external resistor and/or capacitor bias network, as shown in section 10: ?system schematics? . i a analog input analog input for sensing variable voltage levels. os open source open source digital output signal. must be pulled to gnd through an external pull- down resistor. v ref voltage reference input voltage reference input pins required for vddio hstl mode. i pujtag jtag input jtag input pin. includes on-chip pullup to vddio ctl . these pins are 5v tolerant when vddio ctl = 3.3v. for vddio ctl = 2.5v, these pins are up to 4.7v tolerant. o cryst crystal output crystal clock output pin. if not used, leave unconnected. nc no connect no connect signal. must be left floating.
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 19 of 121 9.5 mac transmit interface (mac tx) pins the following pins are used for connecting to a parallel data bus mac via the industry-standard rgmii and rtbi interfaces. table 5. mac tx signal descriptions hsbga ball # signal name mac interface modes type description rgmii rtbi v5, t6, u6, v6 v9, t10, u10, v10 t13, v14, u14, t14 t17, v18, u18, t18 txd[3:0]_3 txd[3:0]_2 txd[3:0]_1 txd[3:0]_0 txd[3:0]_3 txd[3:0]_2 txd[3:0]_1 txd[3:0]_0 i pd multiplexed transmit data nibbles (rgmii mode) bits [3:0] are synchronously input on the rising edge of tx_clk_n, and bits [7:4] on the falling edge of tx_clk_n. multiplexed transmit data nibbles (rtbi mode) bits [3:0] are synchronously input on the rising edge of tx_clk_n, and bits [8:5] on the falling edge of tx_clk_n. u5 u9 v13 u17 tx_ctl_3 tx_ctl_2 tx_ctl_1 tx_ctl_0 txd[4]_3 txd[4]_2 txd[4]_1 txd[4]_0 i pd transmit enable, transmit error multiplexed input (rgmii mode) in rgmii mode, this input is sampled by the phy on opposite edges of tx_clk_n to indicate two transmit conditions of the mac: 1) on the rising edge of tx_clk_n, this input serves as txen, indicating valid data is available on the td input data bus. 2) on the falling edge of tx_clk_n, this input signals a transmit error from the mac, based on a logical derivative of txen and txer, per rgmii specification version 2.0. multiplexed transmit data (rtbi mode) bit [4] is synchronously input on the rising edge of tx_clk_n, and bit [9] on the falling edge of tx_clk_n. t5 t9 u13 v17 tx_clk_3 tx_clk_2 tx_clk_1 tx_clk_0 tx_clk_3 tx_clk_2 tx_clk_1 tx_clk_0 i pd transmit clock input (rgmii mode) the transmit clock shall be either a 125mhz or 25mhz (for 1000mb or 100mb modes, respectively), with a +/-50ppm tolerance. if left uncon- nected, these pins will require a pull-down resistor to ground.
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 20 of 121 9.6 mac receive interface (mac rx) pins all output pins for the mac interface include impedanc e-calibrated, tristateable output drive capability. table 6. mac rx signal descriptions hsbga ball # signal name mac interface modes type description rgmii rtbi v3, t4, u4, v4 v7, t8, u8, v8 v11, v12, u12, t12 t15, v16, u16, t16 rxd[3:0]_3 rxd[3:0]_2 rxd[3:0]_1 rxd[3:0]_0 rxd[3:0]_3 rxd[3:0]_2 rxd[3:0]_1 rxd[3:0]_0 o zc multiplexed receive data nibble (rgmii mode only) bits [3:0] are synchronously output on the rising edge of rx_clk_n, and bits [7:4] on the falling edge of rx_clk_n. multiplexed receive data nibbles (rtbi mode) bits [3:0] are synchronously output on the rising edge of rx_clk_n, and bits [8:5] on the falling edge of rx_clk_n. v2 t7 t11 v15 rx_clk_3 rx_clk_2 rx_clk_1 rx_clk_0 rx_clk_3 rx_clk_2 rx_clk_1 rx_clk_0 o zc receive clock output (rgmii and rtbi modes) receive data is sourced from the phy synchronously on the rising edge of rx_clk_n and is the recovered clock from the media. u3 u7 u11 u15 rx_ctl_3 rx_ctl_2 rx_ctl_1 rx_ctl_0 rxd[4]_3 rxd[4]_2 rxd[4]_1 rxd[4]_0 o zc multiplexed receive data valid / receive error output (rgmii mode only). in rgmii mode, this output is sampled by the mac on opposite edges of rx_clk_n to indicate two receive conditions from the phy: 1) on the rising edge of rx_clk_n, this output serves as rxdv, signal- ing valid data is available on the rd input data bus, 2) on the falling edge of rx_clk_n, th is output signals a receive error from the phy, based on a logical derivative of rxdv and rxer, per rgmii specification version 2.0. multiplexed receive data (rtbi mode) bit [4] is synchronously output on the rising edge of rx_clk_n, and bit [9] on the falling edge of rx_clk_n.
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 21 of 121 9.7 twisted pair interface pins table 7. twisted pair interface pins hsbga ball # signal name type description a6 a10 a14 a18 txvpa_3 txvpa_2 txvpa_1 txvpa_0 a diff tx/rx channel "a" positive signal positive differential signal connected to the posi tive primary side of the transformer. this pin signal forms the positive signal of the "a" data channel. in all three speeds, these pins gener- ate the secondary side signal, normally connected to rj-45 pin 1. see system schematic . b6 b10 b14 b18 txvna_3 txvna_2 txvna_1 txvna_0 a diff tx/rx channel "a" negative signal negative differential signal connected to the ne gative primary side of the transformer. this pin signal forms the negative signal of the "a" data channel. in all three speeds, these pins generate the secondary side signal, normally connected to rj-45 pin 2. see system sche- matic . a5 a9 a13 a17 txvpb_3 txvpb_2 txvpb_1 txvpb_0 a diff tx/rx channel "b" positive signal positive differential signal connected to the posi tive primary side of the transformer. this pin signal forms the positive signal of the "b" data channel. in all three speeds, these pins gener- ate the secondary side signal, normally connected to rj-45 pin 3. see system schematic . b5 b9 b13 b17 txvnb_3 txvnb_2 txvnb_1 txvnb_0 a diff tx/rx channel "b" negative signal negative differential signal connected to the ne gative primary side of the transformer. this pin signal forms the negative signal of the "b" data channel. in all three speeds, these pins generate the secondary side signal, normally connected to rj-45 pin 6. see system sche- matic . a4 a8 a12 a16 txvpc_3 txvpc_2 txvpc_1 txvpc_0 a diff tx/rx channel "c" positive signal positive differential signal connected to the posi tive primary side of the transformer. this pin signals forms the positive signal of the "c" da ta. in 1000mb mode, these pins generate the secondary side signal, normally connected to rj-45 pin 4 (pins not used in 10m/100m modes). see system schematic . b4 b8 b12 b16 txvnc_3 txvnc_2 txvnc_1 txvnc_0 a diff tx/rx channel "c" negative signal negative differential signal connected to the ne gative primary side of the transformer. this pin signal forms the negative signal of the "c" data channel. in 1000mb mode, these pins generate the secondary side signal, normally connected to rj-45 pin 5 (pins not used in 10m/100m modes). see system schematic . a3 a7 a11 a15 txvpd_3 txvpd_2 txvpd_1 txvpd_0 a diff tx/rx channel "d" positive signal positive differential signal connected to the posi tive primary side of the transformer. this pin signal forms the positive signal of the "d" data channel. in 1000mb mode, these pins gener- ate the secondary side signal, normally connected to rj-45 pin 7 (pins not used in 10m/100m modes). see system schematic . b3 b7 b11 b15 txvnd_3 txvnd_2 txvnd_1 txvnd_0 a diff tx/rx channel "d" negative signal negative differential signal connected to the ne gative primary side of the transformer. this pin signal forms the positive signal of the "d" data channel. in 1000mb mode, these pins gen- erate the secondary side signal, normally connected to rj-45 pin 8 (pins not used in 10m/ 100m modes). see system schematic .
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 22 of 121 9.8 serial management interface pins (ieee smi) table 8. serial management interface pins hsbga ball signal name type description p16 mdc i management data clock a 0 to 12.5mhz reference input is used to clock serial mdio data into and out of the vsc8244. the expected nominal frequency is 2.5mhz, as specified by the ieee stan- dard. this clock is typically asynchronous with respect to the phy?s transmit or receive clock. p17 mdio od management data i/o mdio configuration and status data is ex changed on this pin bidirectionally between the phy and the station manager, synchronously to the rising edge of mdc. this sig- nal normally requires a 1.5k to 2k external pull-up resistor at the station manager. the value of the pull-up resistor depends on the mdc clock frequency and the maxi- mum capacitive load on the mdio pin. p18 n16 n17 n18 mdint_0 mdint_1 mdint_2 mdint_3 os/ od management interrupt outputs these output signals indicate a change in each of the four phy?s link operating condi- tions for which a station manager must inte rrogate to determine further information. upon reset or powerup, the vsc8244 will automatically confi gure these pins as active-low (open drain) or active-high (open source) based on the polarity of an exter- nal resistor connection. for active-low conf iguration, tie each mdint_n pin to vdd33 through an external 10k pull-up resistor. for active-high configuration, tie each mdint_n pin to gnd through an external 10k pull-down resistor. if only one mdint_n signal is desired for all four phys, these pins can be tied together on the pcb in a wired -or configuration with only a single pull-up or pull- down resistor.
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 23 of 121 9.9 serial eeprom interface pins 9.10 configuration and control pins table 9. serial ee prom interface pins hsbga ball signal name type description l18 eedat i pd /o eeprom serial data i/o the optional eeprom interface can be used to allow vsc8244 operating mode and configu- ration data to be read from an external eeprom. (the eeprom can also be written if desired.) eeprom data is synchronously exc hanged, bi-directionally, between the vsc8244 and the external eeprom. data is clocked from th e vsc8244 on the fall ing edge of eeclk, and into the vsc8244 on the rising edge of eeclk as defined by the atmel "at24cxxx" type eeproms. this pin should be connected to the sda pin of the eeprom. the vsc8244 determines that an external eeprom is present by monitoring the eedat pin at power-up or when reset is de-asserted: if eedat has a 4.7k external pull-up resistor, the vsc8244 assumes an eeprom is present. the eed at pin can be left floating or grounded to indicate no eeprom. l17 eeclk or pllmode i pd / o zc eeclk - serial eepr om clock output this output is the clock line of the two-wire, serial eeprom interface. the vsc8244 drives this line at a 50 khz rate on reset. when accessed through the mii registers, this line is driven at a 100khz rate. this pin should be connected to the scl pin of the eeprom. pllmode - pllmode - pll mode select input pllmode is sampled during the device power-up sequence or in reset. when pllmode is high, the vsc8244 expects a 125mhz clock input as the phy's reference clock. when pulled low (default), a reference clock of 25mhz is expe cted from either an external crystal or a clock reference input. this pin is internally pulled down with a 100k resistor. table 10. configuration and control pins hsbga ball signal name type description f16 e18 e17 e16 d16 c18 c17 c16 cmode0 cmode1 cmode2 cmode3 cmode4 cmode5 cmode6 cmode7 i a hardware chip mode select the cmode inputs are used for hardware conf iguration of the various operating modes of the vsc8244. each pin has multiple settings, eac h of which is established by an external 1% resistor tied to gnd or vdd33. see section 22.3: ?cmode pin configuration? for details on configuring the vsc8244 with the cmode pins. m16 reset i pu hardware chip reset reset is an active low input, which powers down all of the internal reference voltages and the pll, and resets all internal logic, in cluding the dsps, plls and the mii management register bits are set to their default states. hardware reset is distinct from software rese t which only resets the standard mii registers. m17 soft_reset i pu soft reset soft_reset is an active low input, which places the vsc8244 in a low power state. although the device is powered down; non-vola tile, serial management interface registers retain their values.
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 24 of 121 9.11 system clock interface pins 9.12 led interface pins table 11. system clock interface pins hsbga ball signal name type description r17 clk125 mac o zc reference clock output for mac this pin serves as a 125mhz reference clock output, which can be used to drive a mac or other external device. clk125 mac is powered by the vddio mac supply. this 125mhz clock output pin is enabled by def ault, but can be disabled via an mii register setting. m18 oscen or clk125 micro i pd /o zc oscen - oscillator enable oscen is sampled on the rising edge of reset to determine if the on-chip oscillator is enabled, or an external clock is to be used. when tied high through an external 10k pull-up resistor, the oscillator is enabled, allowin g operation with an external 25mhz crystal. if oscen is tied low (or left floating), the oscill ator circuit is disabled and the device must be supplied with either a 25mhz or 125mhz clock input to refclk (see eeclk or pllmode pin description for more details). clk125 micro - reference clock output for microprocessor this pin serves as a 125mhz or 4mhz refer ence clock output, which can be used to drive a microprocessor or other external device. clk125 micro is powered by the vddio micro supply. this 125mhz or 4mhz clock output pin is disabl ed by default, but can be enabled via an mii register setting. d17 xtal1 or refclk i xtal1 - crystal oscillator input if enabled by oscen high, a 25mhz parallel resonant crystal, with +/-50ppm frequency tol- erance, should be connected across xtal1 and xtal2. 33pf capacitors should be con- nected from xtal1 and xtal2 to ground. pllmode should be left floating (or pulled low) on reset when a 25mhz crystal is used. refclk - phy reference clock input if enabled by oscen low, the reference input clock can either be a 25mhz (pllmode is low) or 125mhz (pllmode is high) referenc e clock, with a +/-50ppm frequency tolerance. see eeclk or pllmode pin description for more details. d18 xtal2 o cryst crystal output 25mhz parallel resonant crystal oscillator output. 33pf capacitors should be connected from both xtal1 and xtal2 to ground when using a crystal. pllmode should be left float- ing (or tied low) on reset when using the 25mhz cr ystal. if not using a crystal, this output pin can be left floating if driving xtal1/refclk with a reference clock. table 12. led interface pins hsbga ball signal name type description a1, d3, e3, f3, g3 c5, c4, c3, b2, a2 g18, g17, g16, f18, f17 j18, j17, h18, h17, h16 led[4:0]_3 led[4:0]_2 led[4:0]_1 led[4:0]_0 o zc led - direct-drive led outputs after reset, these pins serve as the di rect drive, low emi, led driver output pins that can indicate individual status per pin or can be configured to output a serial data stream. all leds are active-low and are powered by the vdd33 power supply. the function of each led pin is configured either through cmode hardware configuration pins (see section 22.3: ?cmode pin config- uration? ) or through mii register 27.
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 25 of 121 9.13 jtag test access port pins 9.14 analog bias pins 9.15 hstl voltage reference pins table 13. jtag tap signal descriptions hsbga ball # signal name type description j16 tdi i pujtag jtag test data serial input data . serial test pattern data is scanned into the device on this input pin, which is sampled with respect to the rising edge of tck. this pin should be tied high during normal chip operation. k16 tdo o zc jtag test data serial output data . serial test data from the vsc8244 is driven out of the device on the falling edge of tck. this pin should be left floating during normal chip opera- tion. k18 tms i pujtag jtag test mode select . this input pin, sampled on the rising edge of tck, controls the tap (test access port) controller?s 16-state, in struction state machine. this pin should be tied high during normal chip operation. k17 tck i pujtag jtag test clock . this input pin is the master clock source used to control all jtag test logic in the device. this pin should be tied high or left floating during normal chip operation. l16 trst i pujtag jtag reset . this active low input pin serves as an asynchronous reset to the jtag tap controller?s state machine. as required by the jtag standard, this pin includes an integrated on-chip pull-up resistor. because of the internal pull-up, if the jtag controller on the printed circuit board does not utilize the trst signal, then the device will still function correctly when the trst pin is left unconnected on the board. alternatively, if the jtag port of the vsc8244 is not used on the printed circuit board, then this pin should be tied to ground (vssio) with a 0 ohm - 4.7k ohm pull-down resistor. table 14. analog bias pins hsbga ball signal name type description c9 ref_rext a bias ref_rext - reference external resistor bias pin connects through external 2k (1%) resistor to analog ground. c10 ref_filt a bias ref_filt - reference filter filter internal reference through external 1 f (10%) capacitor to analog ground. table 15. hstl voltage reference pins hsbga ball signal name type description t3 r8 r10 r13 txref_3 txref_2 txref_1 txref_0 v ref if vddio mac = 1.5v : hstl voltage reference level from mac if vddio mac = 2.5v or 3.3v : tie to gnd. r18 microref v ref if vddio micro = 1.5v : hstl voltage reference level from micro if vddio micro = 2.5v or 3.3v : tie to gnd.
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 26 of 121 9.16 no connect pins 9.17 power supply pins table 16. no connect pins hsbga ball signal name type description b1, c1, c2, c6, c7 c15, d1, d2, e1, e2, e15, f1, g1, g2, h1, h2, j1, j2, k1, l1, l2, m1, m2, n1, n2, p1, r1, r2, t1, t2, u1, u2, v1 nc nc these pins are no connects. do not connect these pins together or to ground. leave these pins unconnected (floating). table 17. power supply pins hsbga ball hsbga supply name type nominal supply voltage (v) description digital i/o power supply pins r5, r6, r7, r9, r11, r12 vddio mac p 3.3v, 2.5v, 1.5v the i/o power supplies on the vsc8244 are separated on the chip itself to facilitate support for different vddio supply volt- ages. these vddio supplies can be run independently at the voltages specified in the previous column. l15 vddio micro p 3.3v, 2.5v, 1.5v k15 vddio ctl p3.3v, 2.5v digital core power supply pins h4, j4, p4, r4, r14, r15, j15, h15 vdddig p 1.2v power for internal digital logic. analog po wer pins d4, l4, g15, f15, d13, d12, d11, d10, d9, d6, d5, c8, r16 vdd33 p 3.3v general 3.3v analog power e4, f4, h3, j3, m3, n3, r3, d15, d14 vdd12 p 1.2v general 1.2v analog power
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 27 of 121 9.18 power supply and associated functional pins ground pins g[7:12], h[7:12], j[7:12], k[7:12], l[7:12], f2, p2, p3, g4, k4, k3, k2, l3, m4, n4, p15, n15, c14, c13, c12, c11, d8, d7 vsss g 0v ground for all blocks except parallel i/o m[7:12], m15 vssio g 0v ground for parallel i/o note: for the 216-pin package this is integrated into the exposed pad. table 18. power supply and associated functional pins power sup- ply pins nominal voltages associated functional pins vddio mac 3.3v, 2.5v, 1.5v txd[3:0], tx_ctl, tx_clk, rxd[3:0] , rx_ctl, rx_clk, txref_n, clk125 mac vddio micro 3.3v, 2.5v, 1.5v soft_reset , reset , mdint_n, mdio, mdc, microref, clk125 micro vddio ctl 3.3v, 2.5v tdi, tdo, tms, tck, trst , eedat, eeclk vdd33 3.3v led[4:0], cmode[7:0], txvn , txvp, ref_rext, ref_filt, xtal1 table 17. power supply pins (continued) hsbga ball hsbga supply name type nominal supply voltage (v) description
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 28 of 121 10 system schematics figure 6. general system schemati c (shown with rgmii and 3.3v i/o) u2 mac controller u3 jtag port controller u4 station manager cpu and/or control logic t1_n transformer u1 vsc8244 port n reset mdint[3:0] microref** tdi tms tck trst txvp_a_n txvn_a_n 1 2 3 6 4 5 7 8 j1_n rj-45 a+ a- b+ b- c+ c- d+ d- s1 s2 rx_ctl_n rx_clk_n txref_n* rxd[3]_n rxd[2]_n rxd[1]_n rxd[0]_n tdi tdo tms tck trst clkin mdio 2k vddio micro 10k vddio micro tx_ctl_n tx_clk_n txd[3]_n txd[2]_n txd[1]_n txd[0]_n microref* phyref reset mdio mdint[3:0] 0.1f 0.1f 0.1f 0.1f 1000pf, 2kv vddio micro vddio ctl vddio mac tx_ctl_n tx_clk_n txd[3]_n txd[2]_n txd[1]_n txd[0]_n txvp_b_n txvn_b_n txvp_c_n txvn_c_n txvp_d_n txvn_d_n 9 10 vddio mac vddio vdd33 digital i/o ref_filt ref_rext gnd 2k (1%) gnd rxd[3]_n 50 rxd[2]_n 50 rxd[1]_n 50 rxd[0]_n 50 rx_ctl_n 50 rx_clk_n 50 txref_n** clk125 mac 50 r t r t r t r t r t r t 75 75 75 75 gnd common analog / digital ground plane 1f 1f tdo 50 mdc vddio r 1 r 1 gnd rx_ref_n eeprom eedat eeclk vddio ctl sda scl soft_reset soft_reset 4 mdc clk125 micro 50 clkin vddio micro r 1 r 1 gnd vdd33 100 100 100 100 100 vdd33 led[3]_n led[2]_n led[1]_n led[0]_n led[4]_n r r cmode[7] cmode[0] ?. 33pf 33pf gnd 25mhz xtal1/refclk xtal2 use a single gnd point for these components (see section on cmode) vdd33 gnd vddio micro vddio ctl ** for hstl only, otherwise connect this inputs to vsss (ground) only available on the 260 pin bga package
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 29 of 121 10.1 input clock options the vsc8244 can be driven by three different clocking schemes providing the end user with desig n flexibility for clock strategy . 10.1.1 crystal clock option a 25mhz crystal can be connected to the xtal1 and xtal2 pins as described in section 9.11: ?system clock interface pins? . the oscen will need to be pulled high and the pllmode can be left floating. please refer to figure 7 figure 7. crystal clock option 10.1.2 25mhz reference clock option a 25mhz reference clock can be connected to xtal1, with xtal2 left floating as described in section 9.11: ?system clock interface pins? . the oscen and the pllmode can be left floating. please refer to figure 8. figure 8. 25 mhz reference clock option 10.1.3 125mhz reference clock option a 125mhz reference clock can be connected to xtal1, with xtal2 left floating as described in section 9.11: ?system clock interface pins? . the oscen can be left floating and the pllmode will need to be pulled high. please refer to figure 9. 33pf 33pf pllmode oscen 10k xtal1/refclk xtal2 3.3v 25mhz reference clock pllmode oscen xtal1/refclk xtal2
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 30 of 121 figure 9. 125 mhz reference clock option 10.2 analog bias pins configuration for proper operation, the vsc8244 must gen erate an on-chip band gap reference voltage at the ref_filt pin. for this, the following components are required for each vsc8244 in the system as specified in section 9.14: ?analog bias pins? . ? 2.00k resistor, 1% tolerance. ? two 1uf capacitors, with 10% tolerance or better. the resistor will connect between the ref_rext pin and ground . one 1uf capacitor will connect between the ref_filt pin and ground. the other capacitor will connect between vdd33 voltage supply and ground. for best performance, special consideration for the ground con nection of the voltage reference circuit is necessary to prevent bus drops which would cause inaccuracy in the reference voltage . each of these ground connections should join together at a small common area and then a short trace should then connect this area to the main ground plane (refer to figure 10). all of these components should be placed as close as possible to the vsc8244. figure 10. analog bias pins ground connection diagram 125mhz reference clock pllmode oscen 10k xtal1/refclk xtal2 3.3v ref_filt ref_rext 1.0uf 1.0uf pcb trace vsc8244 2.00k 1% vdd33 main gnd plane
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 31 of 121 11 mac interfaces 11.1 rgmii mac i/f rgmii mac i/f mode clocks data at 125mhz in 1000bt mode, 25mhz in 100bt mode, or 2.5mhz in 10bt mode. the i/o power supply can be 3.3v, 2.5v, or 1.5v hstl-compliant. figure 11. rgmii mac interface note: ? mac tx lines are usually series- terminated close to the source (at the mac), with r t typically ~22 . ? since the vsc8244 includes on-chip, calibrated, series termi nation resistors, no external series termination resistors are required on the pcb. ? all pcb traces should be 50 controlled impedance traces. ? the vsc8244 includes innovative on-chip timing compensation ci rcuitry to simplify pcb design and layout. please refer to section 25.8.1: "rgmii mode timing" for more information. ? rx_ref should be set to vddio/2 through an external resistor divider network (hstl 1.5v i/o only). ? txref_n is only available in the 260-pin hsbga package ? txref_n should be tied to ground if vddio = 3.3v or 2.5v. ? txref_n should be connected to the mac?s hstl reference when vddio = 1.5v hstl. rgmii mac vsc8244 txd[3]_n txd[2]_n txd[1]_n txd[0]_n tx_clk_n tx_ctl_n rxd[3]_n rxd[2]_n rxd[1]_n rxd[0]_n rx_clk_n rx_ctl_n clk125 mac phy port n td[7]_n/td[3]_n td[6]_n/td[2]_n td[5]_n/td[1]_n td[4]_n/td[0]_n txc_n tx_ctl_n rd[7]_n/rd[3]_n rd[6]_n/rd[2]_n rd[5]_n/rd[1]_n rd[4]_n/rd[0]_n rxc_n rx_ctl_n clk125mhz r t 50 r t r t r t r t r t 50 50 50 50 50 50 r 1 r 1 vddio rx_ref txref_n txref_n
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 32 of 121 11.2 rtbi mac i/f rtbi mac i/f mode, selected by setting the mac i/f selection bits to rtbi mode register 23.15:12 , clocks data at 125mhz. figure 12. rtbi mac interface note: ? mac tx lines are usually terminated on the source side (at the mac), with r t typically ~22 . ? since the vsc8244 includes on-chip, calibrated, series termi nation resistors, no external series termination resistors are required on the pcb. ? all pcb traces should be 50 controlled impedance traces. ? the vsc8244 includes innovative on-chip timing compensation ci rcuitry to simplify pcb design and layout. please refer to section 25.8.2: "rtbi mode timing" for more information. ? rx_ref should be set to vddio/2 through an external resistor divider network (hstl 1.5v i/o only). ? txref_n is only available in the 260-pin hsbga package ? txref_n should be tied to ground if vddio = 3.3v or 2.5v. ? txref_n should be connected to the mac?s hstl reference when vddio = 1.5v hstl. rtbi mac vsc8244 txd[4]_n txd[3]_n txd[2]_n txd[1]_n txd[0]_n tx_clk_n rxd[4]_n rxd[3]_n rxd[2]_n rxd[1]_n rxd[0]_n rx_clk_n clk125 mac td[9]_n/td[4]_n td[8]_n/td[3]_n td[7]_n/td[2]_n td[6]_n/td[1]_n td[5]_n/td[0]_n txc rd[9]_n/rd[4]_n rd[8]_n/rd[3]_n rd[7]_n/rd[2]_n rd[6]_n/rd[1]_n rd[5]_n/rd[0]_n rxc clk125mhz r t r t r t r t r t 50 50 50 50 50 50 r t 50 r 1 r 1 vddio rx_ref phy port n txref_n txref_n
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 33 of 121 12 twisted pair interface the twisted pair interface on the vsc8244 is fully compliant with the ieee802.3-2000 specific ation for cat-5 media. the vsc8244 phy, unlike other traditional gigabit phys, has all passive components (required to connect the phy?s cat-5 interface to an external 1:1 transformer) fully integrated into the device. the connection of the twisted pair interface is sho wn in figure 13: figure 13. twisted pair interface 12.1 twisted pair autonegotiation (ieee802.3 clause 28) the vsc8244 supports twis ted pair autonegotiation , as defined in ieee 802.3-2002 clau se 28. this process evaluates the advertised capabilities of the local phy and its link partner to determine the best possible operating mode. in particular, autonegotiation can determine sp eed, duplex, and master/slave modes for 1000base-t. autonegotiation also allows the local mac to communicate with the link partner mac (via optional ?next-pages?) to set attributes that may not be defined in the standard. if the link partner does not support autonegotiation, t he vsc8244 will automatically use parallel-detect to select th e appropriate link speed. clause 28 twisted-pair autonegotiation can be disabled by clearing mii register bit 0.12 . if autonegotiation is disabled, the operating speed and duplex mode of the vsc8244 is determined by the state of mii register bits 0.6, 0.13 and mii register bit 0.8. vsc8244 txvp_a_n 1 2 3 6 4 5 7 8 j1 rj-45 a+ a- b+ b- c+ c- d+ d- s1 s2 phy port n 1000pf, 2kv 75 75 75 75 0.1f 0.1f 0.1f 0.1f txvn_a_n txvp_b_n txvn_b_n txvp_c_n txvn_c_n txvp_d_n txvn_d_n * * lower cost simpliphy?d magnetics can be utilized.
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 34 of 121 12.2 twisted pair auto mdi/mdi-x function for trouble-free configuration and management of ethernet links, the vsc8244 includes robust automatic crossover detection functionality for all three speeds on the twisted pair inte rface (10base-t, 100base-tx, and 1000base-t) ? fully compliant with the ieee standard. in addition, the vsc8244 detects and corrects po larity errors on all mdi pairs, which is not required by the standard. both the automatic mdi/mdi-x and polarity correcti on functions are enabled by default. however, complete user control of these two features is contained in mii register bit 18.5 and mii register bit 18.4. status bits for each of these functions are indicated in mii register 28. the vsc8244?s automatic mdi/mdi-x algorithm will successfully detect, correct, and operate with any of the mdi wiring pair combinations listed in the following table: 12.3 auto mdi/mdi-x in forced 10/100 link speeds the vsc8244 includes the ability to perform auto mdi/mdi-x even when auto-negotiation is disabled (mii register 0.12 = 0) and the link is forced into 10/100 link speeds. in order to enable this feature, additional mii register write settings are als o needed in the following order: to enable auto mdi/mdi-x in forced 10/100 link speeds: ? write mii register 31 = 0x52b5 ? write mii register 18 = 0x0012 ? write mii register 17 = 0x2803 ? write mii register 16 = 0x87fa ? write mii register 31 = 0x0000 to disable auto mdi/mdi-x in forced 10/100 link speeds: ? write mii register 31 = 0x52b5 ? write mii register 18 = 0x0012 ? write mii register 17 = 0x3003 ? write mii register 16 = 0x87fa ? write mii register 31 = 0x0000 12.4 twisted pair link speed downshift in addition to automatic crossover detection, the vsc8244 supports an automatic link speed ?downshift? option for operation in cabling environments incompatible with 1000base-t. when this feature is enabled, the vsc8244 will automatically change its 1000base-t autonegotiation advertisement to the next slower s peed after a set number of failed attempts at 1000base-t. this is especially useful in setting up networks using older cable installations which may include only pairs a and b and not pairs c and d. the link speed downshift feature is configur ed and monitored through mii register bits 20e.4:1 . table 19. accepted mdi pair connection combinations rj-45 connections comments 1,2 3,6 4,5 7,8 mdi pair connection combinations accepted by vsc8244 a b c d normal mdi mode b a d c normal mdi-x mode abdc mdi mode pair swap on c and d pairs bacd mdi-x mode pair swap on c and d pairs
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 35 of 121 13 transformerless ethernet operation for picmg 2.16 and 3. 0 ip-based backplanes the twisted pair interface supports 10/100/1000bt ethernet for ba ckplane applications such as those specified by the picmg 2.16 and 3.0 specifications for 8-pin channels. with proper ac coupling, the typical category-5 transformer (magnetics) can be removed and replaced with capacitors. for more information, refer to application note: transformerless ethernet concept and applications. by enabling the picmg reduced power mode (mii register bit 24.12 = 1), power consumption can be reduced to under 600mw/ port. for specific backplane applications it is possible for furt her reductions in power consumption (<500 mw/port). to configur e the device for this mode, the following mii register write settings are also needed in the following order: ? write mii register 31 = 0x2a30 ? write mii register 22 = 0x4900 ? write mii register 31 = 0x0000 14 serial management interface (smi) the vsc8244 includes a serial management interface, or ?smi?, t hat is fully compliant with th e ieee 802.3-2000 specifications. the smi interface provides access to various status and control registers within the vsc8244. this mii register set is comprised of a block of thirty-two 16-bit registers, which are segmented into two pages: page0 (main page) and page1 (extended page). the desired register page is selected by setting the page number in register 31. registers 0 through 10, in addition to register 15, (all main page) are required fo r ieee compliance. the vsc8244 implements all ieee-required registers, in addition to several others, providi ng additional performance-monitoring capabilities. see section 24: "mii register descriptions" for more information. the smi is a two pin, synchronous serial interface, with bidirectional data on mdio being clocked on the rising edge of mdc. the smi can be clocked at a rate from 0 to 12.5mhz, depending on the total load on mdio. an external pull-up is required on mdio; it is typically 2k , but depends on the total load on mdio. data is transferred over the smi using 32-bit frames with an optional and arbitrary length preamble. the smi frame format is described in the following table. ?idle : during idle, the mdio node goes to a high-impedance state. this allows an external pull-up resistor to pull the mdio node up to a logical ?1? state. since idle mode should not c ontain any transitions on mdio, the number of bits is undefined during idle. ? preamble : for the vsc8244, the preamble is optional. by default, preambles are not expected or required. the preamble is a string of ?1?s. if it exists, the preamble must be at least one bit, but otherwise may be arbitrarily long. see mii register 1.6 for more information. ? start of frame : a ?01? pattern indicates the start of frame. if these bits are anything other than ?01?, all following bits are ignored until the next ?preamble:0? pattern is detected. table 20. smi frame format direction from vsc8244 preamble start of frame op code phy address register address turn- around data idle # of bits 1+2255216? read output z?s zz zz z?s z?s z0 data z?s input 1?s 01 10 addr addr zz z?s z?s write outputz?szzzzz?sz?szzz?sz?s input 1?s 01 01 addr addr 10 data z?s
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 36 of 121 ? operation code : a ?10? pattern indicates a read. a ?01? pattern indicate s a write. if these bits are anything other than ?01? or ?10?, all following bits are ignored until the next ?preamble? pattern is detected. ? phy address : the next five bits are the phy address. the vsc8244 responds to a message frame only when the received phy address matches its physical address. its physical address has 5 bits, 4:0. bits 4:2 is set by the cmode pin configuration setting. bits 1:0 represent which phy within the device is being addressed. ? register address : the next five bits are the register address. ? turn-around : the next two bits are ?turn-around? (ta) bits. they are used to avoid contention when a read operation is performed on the mdio. during read operations, the vsc8244 will drive the second ta bit, which is a logical ?0?. ?data : the next sixteen bits are data bits. when data is being read from the phy, data is valid at the output of the phy from one rising edge of mdc to the next rising edge of mdc. when data is being written to the phy, data must be valid around the rising edge of mdc. ?idle : the sequence is repeated. the following two figures diagram smi read and smi write operations. figure 14. mdio read frame figure 15. mdio write frame 14.1 smi interrupt the smi includes an output signal mdint_n for signalling the station manager when certain events occur in the phy. a separate mdint_n pin in included for each phy in the vsc8244. each mdint_n pin can be configured for open-drain (active- low), or open-source (active-high) by tying th e pin to either a pull-up resistor to vddio micro (see figure 16 ), or to a pull-down resistor to gnd (see figure 17 ). if only one interrupt pin is required, each mdint_n pin can be tied together to a single pull-up or pull-down resistor in a wired-or configuration. mdc mdio preamble (optional) sfd 1 z10 read 1 0 phy address a4 a3 a2 a1 a0 r4 r3 r2 r1 r0 register address to phy z0 ta register data from phy d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 z z idle idle z station manager drives mdio phy drives mdio mdc mdio preamble (optional) sfd 1 z10 write 01 phy address a4 a3 a2 a1 a0 r4 r3 r2 r1 r0 register address to phy 10 ta register data from phy d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 z z idle idle z station manager drives mdio (phy tristates mdio during entire sequence)
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 37 of 121 figure 16. logical representation of open-drain (active-low) mdint_n pin figure 17. logical representation of open-source (active-high) mdint_n pin when the vsc8244 phy generates an interrupt, the mdint_n pin is asserted (driven either high or low, depending on the external resistor connection) if the interrupt pin enable bit ( mii register 25.15 ) is set. mdint_n (to station manager) interrupt pin enable (mii register 25.15) interrupt pin status (mii register 26.15) external pull-up at station manager for open-drain (active low mode) vddio micro vsc8244 mdint_n mdint_n (to station manager) interrupt pin enable (mii register 25.15) interrupt pin status (mii register 26.15) external pull-down at station manager for open source (active-high mode) vddio micro vsc8244 mdint_n
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 38 of 121 15 parallel led interface the vsc8244 contains dedicated pins to drive 5 leds directly for each phy port. for power savings, all led outputs can be configured to pulse at 5khz with a 20% duty cycl e by setting led pulsing enable (mii register 27.4 = 1). all led outputs are active-low , and driven with 3.3v from the vdd33 power supply. for flexibility, 14 led output functions can be selected for ea ch phy port. these functions are summarized in the following table: table 21. led function assignments led configuration bits mii register bit value led function selection led pin 4 config [1:0] 27.15:14 11 link/activity 10 fault 01 activity 00 duplex/collision led pin 3 config [1:0] 27.13:12 11 rx 10 reserved 01 duplex/collision 00 collision led pin 2 config [1:0] 27.11:10 11 tx 10 link/activity 01 duplex/collision 00 link10/activity led pin 1 config [1:0] 27.9:8 11 link100/1000/activity 10 link/activity 01 link10/100/activity 00 link100/activity led pin 0 config [1:0] 27.7:6 11 rx 10 fault 01 link/act (with serial output on led pins 1 and 2) 00 link1000/activity table 22. led functions function name led state description link1000/activity 1 no link in 1000base-t 0 valid 1000base-t link pulse-stretch/blink 1,2 (optional) valid 1000base-t link and activity present link100/activity 1 no link in 100base-tx 0 valid 100base-tx link pulse-stretch/blink 1,2 (optional) valid 100base-tx link and activity present
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 39 of 121 link10/activity 1 no link in 10base-t 0 valid 10base-t link pulse-stretch/blink 1,2 (optional) valid 10base-t li nk and activity present link10/100/activ- ity 1 no link in 10base-t or 100base-tx 0 valid 10base-t link or valid 100base-tx link pulse-stretch/blink 1,2 (optional) valid 10base-t link or vali d 100base-tx link and activity present link100/1000/ activity 1 no link in 100base-tx or 1000base-t 0 valid 100base-tx link or valid 1000base-t link pulse-stretch/blink 1,2 (optional) valid 100base-tx link or valid 1000base-t link and activity present link/activity 1 no link in any speed 0 valid link in any speed pulse-stretch/blink 1,2 valid link in any speed and activity present collision 1 no collision detected pulse-stretch/blink 2 collision detected activity 1 no activity pulse-stretch/blink 2 activity present fault 1 no ieee clause 28 autonegotiation fault 0 ieee clause 28 autonegotiation fault serial ** see section 16: "serial led output" duplex/collision 1 link established in half-duplex mode, or no link established 0 link established in full-duplex mode pulse-stretch/blink 2,3 (optional) link established in half duplex mode and collisions present rx 1 no activity on rx side pulse-stretch/blink 2 activity present on rx side tx 1 no activity on tx side pulse-stretch/blink 2 activity present on tx side 1 link functions can be combined with activi ty function using an option bit below. 2 function can either blink or be pulse-stretched when acti ve. this behavior is selected using an option bit below. 3 duplex function can be combined with co llision function using an option bit below. table 22. led functions (continued) function name led state description
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 40 of 121 in addition to function selection, several option bits (found in mii register 27) are available for the led outputs. these are summarized below: table 23. led output options led option bits mii register bit value led function selection led blink/pulse-stretch rate 27.5 1 10hz blink rate/ 100ms pulse-stretch 0 5hz blink rate/ 200ms pulse-stretch led pulsing enable 27.4 1 when active, led outputs will be pulsed at 5khz, 20% duty cycle for power savings 0 when active, led outputs will remain at a static low led pulse-stretch/blink select 27.3 1 collision, activity, rx and tx led outputs will be pulse- stretched when active 0 collision, activity, rx and tx led outputs will blink when active led combine link status with activity 27.2 1 link leds indicate link status only 0 link leds will blink or flash when activity is present. blink/ flash behavior is selected by pulse-stretch enable bit. led combine link10/100/1000 with activity 27.1 1 link10, link100, link1000, link10/100, link 100/1000 leds indicate link status only 0 link10, link100, link1000, link10/100, link 100/1000 leds will blink or flash when activity is present. blink/flash behavior is selected by pulse-stretch enable bit. led combine collision with duplex status 27.0 1 duplex led indicates duplex status only 0 duplex led will blink or flash when collision is present. blink/flash behavior is selected by pulse-stretch enable bit.
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 41 of 121 16 serial led output a serial output option is available which allows access to all led signals through two pins. this option is selected by setting led pin 0 configuration bits to 01 on phy0. in this mode, led[1]_0 acts as the serial data pin and led[2]_0 acts as the serial clock pin. these two pins will then output led status for all 4 phys. th e serial mode will clock out the 44 led status bits on the rising edge of the serial clock. the serial bitstream outputs each led signal as as shown in the table below, beginning with phy0 and ending with phy3. the behavior of each led signal is described in table 22 on page 38 . the individual signals shall be clocked out in the following order: table 24. serial led output data phy0 phy1 phy2 phy3 1. link1000/activity 12. link 1000/activity 23. link1000/ac tivity 34. link1000/activity 2. link/activity 13. link/activity 24. link/activity 35. link/activity 3. link100/activity 14. link100/activity 25. link100/activity 36. link100/activity 4. activity 15. activity 26. activity 37. activity 5. link10/activity 16. link10/activity 27. link10/activity 38. link10/activity 6. duplex/collision 17. duplex/collision 28. duplex/collision 39. duplex/collision 7. tx 18. tx 29. tx 40. tx 8. collision 19. collision 30. collision 41. collision 9. rx 20. rx 31. rx 42. rx 10. fault 21. fault 32. fault 43. fault 11. reserved 22. reserved 33. reserved 44. reserved
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 42 of 121 17 test mode interface (jtag) the vsc8244 supports the test access port and boundary scan architecture ieee 1149.1 standards. the device includes an ieee 1149.1 conformant test interface, oft en referred to as a ?jtag tap interface?. ieee 1149.1 defines test logic to provide standardized test methodologies for: ? testing the interconnections between integrated circuits on ce they have been assembled onto a printed circuit board or other substrate ? testing the integrated circuit itself during ic and systems manufacture ? observing or modifying circuit activity during the component?s normal operation the jtag test interface logic on the vsc8244, accessed through a test access port (tap) interface, consists of a boundary- scan register and other logic co ntrol blocks. the tap controller includes all i eee-required signals (tms, tck, tdi, and tdo), in addition to the optional asynchronous reset signal trst . refer to jtag tap signal descriptions section for additional information about these pins. the following figure diagrams the tap and boundary scan architecture. figure 18. test access port and boundary scan architecture the vsc8244 also includes the optional device identification register, shown in the following table, which allows the manufacturer, part number, and version number of the device to be determined through the tap controller. boundary-scan register device identification register bypass register instruction register, instruction decode, control test access port controller trst# tms tdi tck select control tdoenable control mux, dff tdo
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 43 of 121 see chapter 11 of the ieee 1149.1-1990 specifications for mo re details. also, note that some of the information in the identification register is duplicated in the ieee-specified bit fields in mii register 3 (phy identifier register #2) . 17.1 supported instructions and instruction codes after a tap reset, the device identification register is serially connected between tdi and tdo by default. the tap instruction register is loaded either from a shift register (when a new instru ction is shifted in), or, if there is no new instruction in t he shift register, a hard-wired default value of 0110 (idcode) is loaded. using this method, there is always a valid code in the instruction register, and the problem of toggling instruction bits during a shift is avoided. unused codes are mapped to the bypass instruction. the vsc8244 supports the instruction codes listed in the following and described below. extest the mandatory extest instruction allows testing of off-chip circuitry and board-level interconnections by sampling input pins and loading data onto output pins. outputs are driven by the cont ents of the boundary-scan cells, which have to be updated with valid values (with the preload instruction) prior to the extest instruction. sample/preload the mandatory sample/preload instruction allows a snapshot of inputs and outputs during normal system operation to be taken and examined. it also allows data values to be loaded into the boundary-scan cells prior to the selection of other boundary-scan test instructions. idcode the optional idcode instruction provides the version number (bits 31:28), part number (bits 27:12), and vitesse?s manufacturer identity (bits 11:1) to be serially read from the vsc8244. see table 25: ?jtag device identification register description? for the vsc8244-specific values for this instruction. clamp the optional clamp instruction allows the state of the signals driven from the component pins to be determined from the table 25. jtag device identi fication register description description device version number (or revision code) part number (or model number) vitesse?s manufacturer identity lsb bit field 31 - 28 27 - 12 11 - 1 0 binary value silicon revision c = 0010 1000 0010 0100 0100 001 1001 1000 1 table 26. jtag interface instruction codes instruction code selected register register width specification extest 0000 boundary-scan register 196 mandatory ieee 1149.1 sample/preload 0001 boundary-scan register 196 mandatory ieee 1149.1 idcode 0110 device identification register 32 optio nal ieee 1149.1 clamp 0010 bypass register 1 optional ieee 1149.1 highz 0011 bypass register 1 optional ieee 1149.1 bypass 0111 bypass register 1 mandatory ieee 1149.1 nandtest 0101 bypass register 1 optional ieee 1149.1 reserved 0100, 1000 - 1111
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 44 of 121 boundary-scan register while the bypass register is selected as the serial path between tdi and tdo. while the clamp instruction is selected, the signals driven from the component pins will not change. 1 highz the optional highz instruction places the component in a state in which all of its system logic out puts are placed in a high impedance state. in this state, an in-circuit test system ma y drive signals onto the connections normally driven by a component output without incurring a risk of damage to the component. this makes it possible to use a board where not all of the components are compatible with the ieee 1149.1 standard. 1 bypass the bypass register contains a single shift-register stage and is used to provide a minimum-l ength serial path (one tck clock period) between tdi and tdo to bypass the device when no test operation is required. nandtest nandtest is an internal command used to activate the nand tree test mode. 17.2 boundary-scan register cell order all inputs and outputs are observed in the boundary-scan register cells. all outputs are additionally driven by the contents of boundary-scan register cells. bidirectional pins have all three related boundary-scan register cells: the input, the output, an d the control. the full boundary scan cell order is available as a .bsd file format. 1 following the use of this instruction, the on-chip system logic may be in an indetermina te state that will persist until a syst em reset is applied. therefore, the on-chip system logic must be reset on return to normal (i.e., non-test) operation.
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 45 of 121 18 veriphy cable diagnostics the vsc8244 provides a comprehensive suite of cable diagnostic functions that are available through smi reads and writes. vitesse provides a library of routines that enable a variety of cable operating conditions and status to be accessed. these functions have the ability to identify the cable length and operating conditions, and to isolate a variety of common faults tha t can occur on the cat-5 twisted pair cabling. contact vitesse semiconductor for access to the veriphy? library of routines. the following functions are available: ? coupling between cable pairs ? cable pair termination ? cable length ? using veriphy? in normal operating mode 18.1 coupling between cable pairs anomalous coupling between cable pairs can be caused by shorted wi res, improper termination, or high crosstalk resulting from an incorrect wire map. these conditions can all prevent the vsc8244 from establishing a link in any speed. 18.2 cable pair termination proper termination of cat-5 cable requires a 100-ohm differential impedance between the positive and negative cable terminals. ieee802.3 allows for a termination of as high as 1 15-ohms or as low as 85-ohms. if the termination falls outside of this range, it will be reported as an anomalous termination by the veriphy ? cable diagnostics. the diagnostics can also determine the presence of an open or shorted cable pair. 18.3 cable length when properly terminated, veriphy reports the approximate cable le ngth in meters for each of the four cable pairs a, b, c, and d. 18.4 using veriphy in normal operating mode if a link is established on the twisted pair interface in 1000base-t mode, the veriphy ? cable diagnostics can run without disruption of the link or of any data transfer. however, if a link is es tablished in 100base-tx or 10base-t, the veriphy ? cable diagnostics will cause the link to drop while the diagnostics are running. once the diagnostics are finished, the link will be reestablished.
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 46 of 121 19 actiphy power management in addition to the ieee-specified power-d own control bit (mii register 0.11), the vsc8244 implements an actiphy? power management mode. this mode enables support for power-sensitiv e applications such as laptop computers with wake-on- lan? capability. it utilizes a signal-detect function that monitors the media interface for the presence of a link to determine when to automatically power-down the phy. the phy ?wakes up? at a programmable interval and attempts to ?wake-up? the link partner phy by sending either a fast link pulse (flp) over copper media. the actiphy? power management mode can be set at any time on a per port basis during normal operation by setting mii register 28.6 = 1. when actiphy? is enabled and the phy is in the ?low power? or ?lp wake-up? states, by default a 25mhz clock signal is sent out on the rx_clk pin. this function can be disabled by setting mii register bit 23.5 = 0. 19.1 operation in actiphy mode there are three phy operating states when enhanced actiphy ? mode is enabled: ? low power state ? lp wake up state ? normal operating state (link up state) the phy switches between the low power state and lp wake up state at a programmable rate (sleep timer) until signal energy has been detected on the media interface pins. when signal energy is detected, the phy enters the normal operating state. when the phy is in the normal operating state and link is lost, the phy returns to the low power state after the link status ti me- out timer has expired. after reset, the phy enters the low power state. when autonegotiation is enabled in the phy, the actiphy? state machine will operate as described above. if autonegotiation is disabled and the link forced to 10bt or 100btx modes while the phy is in the low power state, the phy continues to transition between the low power and lp wake up states until signal energy is detected on the media pins. at that time, the phy transitions to the normal operating state and stays in that state even when the link is dropped. if autonegotiation is disabled while the phy is in the normal operation state, the phy stays in that state when the link is dropped and does not transition ba ck to the low power state. figure 19. actiphy state diagram low power state lp wake-up state normal operation flp signal sent sleep timer expires timeout timer expires and auto-negotiation enabled signal energy detected on media
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 47 of 121 19.2 low power state in the low power state, all major digi tal blocks are powered down. however the following functionality is provided: ? smi interface (mdc, mdio, mdint _n) ? clk125 mac and clk125 micro in this state, the phy monitors the media interface pins for signal energy. the phy comes out of low power state and transition s to the normal operating state when signal energy is detected on the media. this happens when the phy is connected to one of the following: ? auto-negotiation capable link partner ? auto-negotiation incapable (blind/forced) 100btx only link partner ? auto-negotiation incapable (blind/forced) 10bt only link partner ? another phy in enhanced actiphy lp wake up state in the absence of signal energy on the media pins, the phy will transition from the low power state to the lp wake up state periodically based on the programmable sleep timer. two register bi ts (mii register bits 28.1:0) are provided to program the value of the sleep timer. the sleep timer can be programmed to 00 (1second), 01 (2 seconds), 10 (3 seconds) or 11 (4 seconds). the default value is 2 seconds. the actual sleep time duration is randomized by -80ms to +60ms to avoid two linked phys in actiphy tm mode from entering a lock-up state. 19.3 lp wake up state in this state, the phy attempts to wake up the link partner. one complete flp (fast link pulse) is sent on both pairs a and b o f the cat5 media. in this state the following functionality is provided- ? smi interface (mdc, mdio, mdint _n) ? clk125 mac and clk125 micro after sending signal energy on the relevant media, the phy returns to the low power state. 19.4 normal operating state in this state, the phy establishes a link with a link partner. when the media is unplugged or the link partner is powered down, the phy waits for the duration programmed through a link status time-out timer and then enters the low power state. the link status time-out timer can be programmed to 00 (1second), 01 (2 seconds), 10 (3 seconds) or 11 (4 seconds). the default value for this timer is 2 seconds.
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 48 of 121 20 ethernet in-line powered device support 20.1 cisco in-line powered device detection this feature is used for detecting in-line powered devices in ethernet network applications. the vsc8244's in-line powered device detection mode can be part of a syst em that allows for ip-pho ne and other devices such as wireless access points to receive power from an ethernet cable, si milar to office digital phones receiving power from a pbx (private branch exchange) office switch via the phone cable. this can eliminate the need for an ip-phone to have an external power supply since the ethernet cable provides power. it also enables the in-line powered device to remain active during a power outage (assuming the ethernet switch is connected to an uninterrupted power supply, battery, back-up power generator, etc). each of the 4 phys can independently perform in-line power detection. this mode is disabled by default and must be enabled for each phy in order to perform in-line powered device detection. please refer to additional information at http://www.cisco.com/en/us/ products/hw/phones/ps379/products_tech_note09186a00801189b5.shtml . 20.2 in-line power et hernet switch diagram figure 20. in-line powered ethernet switch diagram smi control processor gigabit switch vsc8244 quad 10/100/ 1000bt phy rgmii interface vsc8244 quad 10/100/ 1000bt phy x-former rj-45 i/f vsc8244 quad 10/100/ 1000bt phy x-former rj-45 i/f x-former rj-45 i/f in-line power supply unit cat-5
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 49 of 121 20.3 in-line powered device detection (cisco method) this section describes the flow process an ethernet switch must perform in order to process in-line power requests made by a link partner (lp) capable of receiving in-line power. 1. the in-line powered device detection mode is enabled on each phy through the serial management interface by setting mii register bit 23e.10 = 1 and ensuring auto-negotiation enable bit (mii register 0.12) = 1. the phy will then start sending a special fast link pulse (flp) signal to the lp. mii regist er 23e.9:8 will equal 00 during the search for devices needing in-line power. 2. the phy monitors for the special flp signal looped back by the lp. an lp device capable of receiving in-line power will loopback the special flp pulses when it is in a powered-down state. this is reported when mii register 23e.9:8 = 01. this can be verified as an in-line power detection interrupt by reading mii register 26.9 = 1, which will subsequently be cleared and the interrupt de-asserted after the read. if an lp device does not loopback the special flp after a specific time, then mii register 23e.9:8 = 10. 3. if the phy reports that the lp needs in-line power then the ethernet switch needs to enable in-line power on this port exter- nally of the phy. 4. the phy automatically disables in-line powered device detection after event #3 above and now changes to the normal auto-negotiation process. a link is then auto-negotiated and es tablished when the link status is set (mii register bit 1.2 = 1) 5. in the event of a link down event (mii register bit 1.2 = 0), the in-line power should be disabled to the in-line powered device external to the phy. the phy will disable the normal auto-negotiation process and re-enable in-line powered device detection mode. 20.4 ieee 802.3af (dte power via mdi) the vsc8244 is fully compatible with switch designs which are in tended for use in systems that su pply power to the dte (data terminal equipment) via the mdi (media dependent interface, or twisted pair cable), as specified by ieee 802.3af standard (clause 33). 21 advanced test modes 21.1 ethernet pa cket generator (epg) for system-level debugging and in-system production test ing, the vsc8244 includes an ethernet packet generator for 1000base-t testing. this can be used to isolate problems between the mac and phy and between a local phy and remote link partner. it is intended for use with lab testing equipment or in-system test equipment only, and should not be used when t he vsc8244 is connected to a live network. to use the epg, it must be enabled by writing a ?1? to mii regist er 29e.15. this effectively disables all mac-interface transmi t pins and selects the epg as the source for all data transmitted onto the vsc8244 twisted pair interface. for this reason, packe t loss will occur if the epg is enabled during transmission of packets from mac to phy. the mac receive pins will still be active when the epg is enabled, however. if it is necessary to disable the mac receive pins as well, this can be done by writing a ?1? to mii register bit 0.10. when a ?1? is written to mii register bit 29e.14 , the vsc8244 will begin transmitting ieee802.3 layer-2 compliant packets with a data pattern of repeating 16-bit set by mii register 30e. the source and destination addresses for each packet, packet size, interpacket gap, fcs state and transmit duration can all be controlled through mii register 29e . note that if mii register bit 29e.13 is cleared, mii register bit 29e.14 will be cleared automatically after 30,000,000 packets have been transmitted. 21.2 crc counter a bad-crc counter is also available for all incoming pa ckets for 1000base-t mode. this counter is available in mii register bits 23e.7:0 - 1000bt crc counter and is automatically cleared when read.
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 50 of 121 21.3 far-end loopback far-end loopback mode when enabled (mii register bit 23.3 = 1) forces incoming data from a link partner on the current media interface to be retransmitted back to the link partner on the media interface as shown in figure 21 . in addition, the incoming data will also appear on the receive data pins of the mac interface. data present on the transmit data pins of the mac interfac e are ignored in this mode. for more information, please refer to mii register 23 . figure 21. far-end loopback block diagram 21.4 near-end loopback when near-end loopback is set (mii register bit 0.14 = 1), the transmit data (txd) on the mac interface is looped back onto the receive data (rxd) pins to the mac as shown in figure 22 . in this mode, no signal is transmitted over the network media. figure 22. near-end loopback block diagram link partner vsc8244 mac rx tx rxd txd cat-5 link partner vsc8244 mac rx tx rxd txd cat-5
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 51 of 121 21.5 connector loopback connector loopback allows for the twisted pair interface to be looped back externally. in this mode, the phy must be connected to a loopback connector or a loopback cable. for this loopback, pair a should be connected to pair b and pair c to pair d. this loopback will work in all speeds selected for the interface. figure 23. connector loopback the autonegotiation, speed, and duplex can be configured using mii registers 0, 4, and 9. for 1000bt connector loopback only the following additional writes ar e required in the specified order. 1. master/slave configuration forced to master (mii register bits 9.12:11 = 11) 2. enable 1000bt connector loopback (mii register bit 24.0 = 1) 3. disable pair swap correction (mii register bit 18.5 = 1) 4. disable autonegotiation and force 1000bt link (mii register bit 0.12 = 0, mii register bit 0.6 = 1, and mii register bit 0.13 = 0) and force either full or half duplex (mii register bit 0.8 = 0 or 1). phy_n mac rxd txd cat-5 a b c d
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 52 of 121 22 initialization & configuration 22.1 resets there are four conditions which can cause a reset of some or all parts of the vsc8244: device power-up: on device power-up, the vsc8244 first reads the status of the cmode hardware configuration and sets the appropriate mii register bits. all mii register bits not associated to a cmode hardware configuration are then reset to their default values. the last step in power-up before the device becomes active is a re ad of eeprom configur ation, if an eeprom is present. note that because it is the la st step in the reset sequence, it is possi ble for the eeprom to overwrite mii registe r bits previously set by cmode hardware configuration. device hardware reset: a complete hardware reset of all four phys in the vsc8244 occurs on the rising edge of the reset pin. this functions identically to device power-up, above. device software reset: a complete software reset of all four phys in the vsc8244 occurs on the rising edge of the soft_reset pin. when this occurs, a ll mii register bits not marked as ?sticky? will be reset to thei r default values. if mii register bit 21e.14 is set to a ?1?, the eeprom configuration data will be read next , if one is present. phy software reset through mii register bit 0.15: an individual phy reset can be initiated by writing a ?1? to mii register bit 0.15 . this functions identically to device software reset, except that it only affects a single phy in the vsc8244. 22.2 power-up sequence the power supply sequence to the vsc8244 may be powered in any order. 22.3 cmode pin configuration eight cmode (configuration mode) pins are used by the device to provide a flexible method of hardware configuration without the need for a microcontroller or station manager. each cmode pin maps to four configuration bits giving one pin control of 16 possible default settings. this is controlled by connecting th e cmode pins to either vdd 33 or vsss (ground) through an external 1% resistor as shown in table 28. as a result, 32 total configuration bits settings at power-up are possible within the 8 cmode pins as shown in table 27. the resistors used on the cmode pins can be considered optional for designs that have access to the vsc8244?s management interface. in this manner all configurations pres ent in cmode can be altered via mii register settings and the cmode pins can be pulled to vsss (ground). however, the only feature that still requires cmode configuration is the phyaddr[4:2] selection. this can be set by either tieing these pins to vdd33 or vsss.
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 53 of 121 22.3.1 cmode hardware configuration bits 32 cmode hardware configuration bits are mapped to the 8 cmode pins as shown in the following table: 22.3.2 setting the cmode configuration bits the cmode pins are set by connecting the cmode pins to eith er vdd33 or vsss (ground) through an external 1% resistor. to set the cmode pins to utilize the 32 cmode configuration bits, please refer to the following combination table below: table 27. cmode hardwa re configuration bits cmode pin # bit 3 function (msb) bit 2 function bit 1 function bit 0 function (lsb) 7 rgmii clock skew[1] always set to logic ?0? actiphy link speed downshift 6 rgmii clock skew[0] always se t to logic ?0? led combine link/act led pulse-stretch/blink 5 phy address [4] always set to logic ?0? led combine link10/ 100/1000/act led combine col/dup 4 phy address [3] speed/dup modes [1] led4[1] led4[0] 3 phy address[2] speed/dup modes [0] led3[1] led3[0] 2 mac interface [2] always set to logic ?0? led2[1] led2[0] 1 mac interface [1] pause control[1] led1[1] led1[0] 0 always set to logic ?1? pause control[0] led0[1] led0[0] table 28. cmode pin combinations cmode bit 3 value cmode bit 2 value cmode bit 1 value cmode bit 0 value cmode resistor value tied to vdd or gnd 00000gnd 0 0 0 1 2.26k gnd 0 0 1 0 4.02k gnd 0 0 1 1 5.90k gnd 010 0 8.25k gnd 010112.1kgnd 011016.9kgnd 011122.6kgnd 10000vdd33 1 0 0 1 2.26k vdd33 1 0 1 0 4.02k vdd33 1 0 1 1 5.90k vdd33 1 1 0 0 8.25k vdd33 110112.1kvdd33 111016.9kvdd33 111122.6kvdd33
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 54 of 121 22.3.3 hardware configuration bit description the function for each cmode configuration bit shown in table 27 is described in the following table: table 29. cmode configuration bits name sets mii register value description mac-side interface select [2:1] 23.14:12, 23.2:1 11 rgmii to cat5 10 reserved 01 reserved 00 rtbi to cat5 (please refer to register 23 for additional settings required). phy address [4:2] n/a xxx 3 msbs of phy address actiphy tm 28.6 1 enable actiphy tm power management 0 disable actiphy tm power management ledn[1:0] 27.15:6 xx mapped directly to the two function selection bits for each led pin. (see mii register 27 for more information) led pulse-stretch/blink select 27.3 1 collision, activity, rx and tx led outputs will be pulse-stretched when active 0 collision, activity, rx and tx led outputs will blink when active led combine link with activity 27.2 1 link leds indicate link status only 0 link leds will blink or flash when activity is present. blink/flash behavior is selected by pulse-stretch enable bit. led combine link10/100/1000 with activity 27.1 1 link10, link100, link1000, link10/100, link100/1000 leds indicate link status only 0 link10, link100, link1000, link10 /100, link100/1000 leds will blink or flash when activity is present. blink/flash behavior is selected by pulse-stretch enable bit. led combine collision with duplex 27.0 1 duplex led indicates duplex status only 0 duplex led will blink or flash when collision is present. blink/flash behavior is selected by pulse-stretch enable bit. speed/duplex autonegotiation advertisement 4.8:5, 9.9:8 11 10/100base-t, hdx, fdx 10 1000base-t, fdx 01 10/100/1000base-t, fdx; 10/100base-t hdx 00 10/100/1000base-t, hdx, fdx link speed downshift 20e.4 1 enable link speed downshift capability on 2-pair cable or after 3 failed autonegotiation attempts 0 link only according to autonegotiation resolution pause control [1:0] 4.11:10 xx pause control autonegotiation advertisement rgmii skew [1:0] 1 1 to independently control the rx_clk and tx_clk rgmii skew please refer to mii register 23 for more information. 23.11:8 11 2.5ns skew on rx_clk and tx_clk 10 2ns skew on rx_clk and tx_clk 01 1.5ns skew on rx_clk and tx_clk 00 no skew on rx_clk and tx_clk
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 55 of 121 22.4 eeprom interface the optional eeprom interface on the vsc8244 provides the phy with the ability to self configure its internal registers. the eeprom is read on powerup or deassertion of reset . the eeprom can also be accessed through mii registers for field configurability. the optional eeprom must have a two-wire interface such as atmel "at24cxxx" in order to interface to the vsc8244. as defined by this interface, data is clocked from the vsc8244 on the falling edge of eeclk. the vsc8244 determines that an external eeprom is present by monitoring the eedat pin at powerup or when reset is de-asserted. if eedat is connected to a 4.7k external pull-up resistor, the vsc 8244 assumes an eeprom is present. the eedat pin can be left floating or grounded to indicate no eeprom. if the vsc8244 detects an eeprom present, then mii register bit 23.0 = 1 otherwise it will be cleared. 22.4.1 eeprom contents description if an eeprom is present, the start-up control block looks for a ?vitesse header? 0xbdbd at address 0 & 1 of the eeprom. the address is incremented by 256 until the vitesse header is found. if the vitesse header is not found, or no eeprom is connected, the vsc 8244 bypasses the eeprom read step. once the 'header value' is found, then the following two byte address values in dicates the eeprom word address where the configuration contents for the vsc8244 are located. at the base address location the next 10 bytes indicate where the configuration data contents to be programmed into the vsc8244 are located. the first address points to the data common to all phys. each subsequent address location points to each individual phy?s configuration contents. at each programming location the two bytes represent the total number of bytes (11 bits long , with msb first) where total_number_bytes[10:0] = number of smi writes x 3 (1 byte for smi port & reg address & 2 bytes fo r data). refer to table below. data is read from the eeprom sequentially (at 50 khz, or 50 kbits/s) until all smi write commands are completed. if an eeprom is present, but the eeprom does not acknowledge (according to the atmel ee prom protocol ), the vsc8244 waits for an acknowledge for approximately 3 seconds. if ther e is no acknowledge for 3 seconds, the vsc8244 will abort and continue into normal operation. table 30. eeprom configuration contents 10-bit address contents (bits 7:0) 00xbd 10xbd 2 phy_addr[4:2], 00, base_address_location[10:8] 3 base_address_location[7:0] (k) ------------- ---------------------------------------------------- ------------- ---------------------------------------------------- k 00000, common_config_base_address[10:8] k+1 common_config_base_address[7:0] (x) k+2 00000, phy0_specific_config_base_address[10:8] k+3 phy0_specific_config_base_address[7:0] (y) k+4 00000, phy1_specific_configuration_address[10:8] k+5 phy1_specific_config_base_address[7:0] k+6 00000, phy2_specific_config_base_address[10:8] k+7 phy2_specific_config_base_address[7:0] k+8 00000, phy3_specific_config_base_address[10:8] k+9 phy3_specific_config_base_address[7:0] ------------- ----------------------------------------------------
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 56 of 121 22.4.2 programming multiple vsc8244 using the same eeprom when the same eeprom is used to initiali ze multiple vsc8244 devices, to prevent contention on the 2 wire bus, the eeprom start-up block of each vsc8244 will monitor the bus for (phyaddr ess[4:2] + 1)* 9 clock cycles for no bus activity and only then attempt to access the bus. phyaddress[4:2] is chosen because these are the phyaddress bits that are unique to each vsc8244. (i.e vsc8244s with lower phyaddress get priority in the bus.) note: it is important that multiple vsc8244's refclk pi ns use the same clock. in addition, all vsc8244's reset pins be asserted and deasserted simultaneously to ensure that the reference clock modes within each device are correctly set. this prevents having one vsc8244 use the output of a clk125 mac or clk125 micro pin from another vsc8244 as a clock reference if the devices are sharing the same eeprom. note: the above scheme for preventing bus contention will wo rk only when multiple vsc8244 devices accessing the eeprom have unique phyaddress[4:2] values. ------------- ---------------------------------------------------- x 00000, total_number_bytes[10:8] x+1 total_number_bytes[7:0] (m) x+2 register address a x+3 data [15:8] to be written to register address a x+4 data [7:0] to be written to register address a x+5 register address b x+6 data [15:8] to be written to register address b x+7 data [7:0] to be written to register address b ------------- ---------------------------------------------------- x+(m-2) register address x x+(m-1) data [15:8] to be written to register address x x+m data [7:0] to be written to register address x ------------- ---------------------------------------------------- ------------- ---------------------------------------------------- y 00000, total_number_bytes[10:8] y+1 total_number_bytes[7:0] (n) y+2 register address a y+3 data [15:8] to be written to register address a y+4 data [7:0] to be written to register address a ------------- ---------------------------------------------------- y+(n-2) register address x y+(n-1) data [15:8] to be written to register address x y+n data [7:0] to be written to register address x ------------- ---------------------------------------------------- ------------- ---------------------------------------------------- max address ---------------------------------------------------- table 30. eeprom configuration contents (continued) 10-bit address contents (bits 7:0)
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 57 of 121 figure 24. vsc8244 devices connect ed to use the same startup eeprom table 31. eeprom configuration cont ents for multiple vsc8244 devices 10-bit address contents (bits 7:0) 00xbd 10xbd 2 phy_addr[4:2], 00, base_address_location[10:8] 3 base_address_location[7:0] (for vsc8244 a) 4 phy_addr[4:2], 00, base_address_location[10:8] 5 base_address_location[7:0] (for vsc8244 b) 6 phy_addr[4:2], 00, base_address_location[10:8] 7 base_address_location[7:0] (for vsc8244 c) ------------- ---------------------------------------------------- ------------- ---------------------------------------------------- a 00000, common_a_config_base_address[10:8] a+1 common_a_config_base_address[7:0] (x) a+2 00000, phy0_a_specific_config_base_address[10:8] a+3 phy0_a_specific_config_base_address[7:0] a+4 00000, phy1_a_specific_configuration_address[10:8] a+5 phy1_a_specific_config_base_address[7:0] a+6 00000, phy2_a_specific_config_base_address[10:8] a+7 phy2_a_specific_config_base_address[7:0] a+8 00000, phy3_a_specific_config_base_address[10:8] a+9 phy3_a_specific_config_base_address[7:0] ------------- ---------------------------------------------------- ------------- ---------------------------------------------------- smi 3 smi 0 smi 2 smi 1 eeprom reader eeprom mdc mdio vsc8244 (a) vsc8244 (b) vsc8244 (c) eeclk eedat
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 58 of 121 b 00000, common_b_config_base_address[10:8] b+1 common_b_config_base_address[7:0] (y) b+2 00000, phy0_b_specific_config_base_address[10:8] b+3 phy0_b_specific_config_base_address[7:0] b+4 00000, phy1_b_specific_configuration_address[10:8] b+5 phy1_b_specific_config_base_address[7:0] b+6 00000, phy2_b_specific_config_base_address[10:8] b+7 phy2_b_specific_config_base_address[7:0] b+8 00000, phy3_b_specific_config_base_address[10:8] b+9 phy3_b_specific_config_base_address[7:0] ------------- ---------------------------------------------------- ------------- ---------------------------------------------------- c 00000, common_c_config_base_address[10:8] c+1 common_c_config_base_address[7:0] (z) c+2 00000, phy0_c_specific_config_base_address[10:8] c+3 phy0_c_specific_config_base_address[7:0] c+4 00000, phy1_c_specific_configuration_address[10:8] c+5 phy1_c_specific_config_base_address[7:0] c+6 00000, phy2_c_specific_config_base_address[10:8] c+7 phy2_c_specific_config_base_address[7:0] c+8 00000, phy3_c_specific_config_base_address[10:8] c+9 phy3_c_specific_config_base_address[7:0] ------------- ---------------------------------------------------- ------------- ---------------------------------------------------- x 00000, total_number_bytes[10:8] x+1 total_number_bytes[7:0] (n) x+2 register address a x+3 data [15:8] to be written to register address a x+4 data [7:0] to be written to register address a x+5 register address b x+6 data [15:8] to be written to register address b x+7 data [7:0] to be written to register address b ------------- ---------------------------------------------------- x+(n-2) register address x x+(n-1) data [15:8] to be written to register address x x+n data [7:0] to be written to register address x ------------- ---------------------------------------------------- ------------- ---------------------------------------------------- y 00000, total_number_bytes[10:8] table 31. eeprom configuration cont ents for multiple vsc8244 devices (continued) 10-bit address contents (bits 7:0)
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 59 of 121 with the above scheme for eeprom contents , if multiple vsc8244 devices are initiali zed in a similar way, the base address locations can each point to the same address location from the eeprom. if they have to be initialized differently, then each base location will differ for each device and the data contents to be configured for each will be unique. 22.4.3 read/write access to the eeprom the vsc8244 has the ability to read and write to an eeprom (such as an atmel at24cxxx) connected to the eeclk and eedat pins of the device. if it is required to be able to wr ite to the eeprom, please refer to the eeprom?s specific datasheet to ensure that write protec tion on the eeprom is not set. to read a value from a specific address of the eeprom, first re ad mii register bit 21e.11 and ensure that it is set. after confirming this bit is set, write the address to be read to m ii register bits 21e.10:0, set mii register bit 21e.12 = 1, and th en set mii register bit 21e.13 = 1. wait until 21e.11 = 1 and then read the 8-bit data value found at 22e.15:8 that contains the conte nts of the address just read by the phy. y+1 total_number_bytes[7:0] (m) y+2 register address a y+3 data [15:8] to be written to register address a y+4 data [7:0] to be written to register address a y+5 register address b y+6 data [15:8] to be written to register address b y+7 data [7:0] to be written to register address b ------------- ---------------------------------------------------- y+(m-2) register address x y+(m-1) data [15:8] to be written to register address x y+m data [7:0] to be written to register address x ------------- ---------------------------------------------------- ------------- ---------------------------------------------------- z 00000, total_number_bytes[10:8] z+1 total_number_bytes[7:0] (p) z+2 register address a z+3 data [15:8] to be written to register address a z+4 data [7:0] to be written to register address a z+5 register address b z+6 data [15:8] to be written to register address b z+7 data [7:0] to be written to register address b ------------- ---------------------------------------------------- z+(p-2) register address x z+(p-1) data [15:8] to be written to register address x z+p data [7:0] to be written to register address x ------------- ---------------------------------------------------- ------------- ---------------------------------------------------- max address ---------------------------------------------------- table 31. eeprom configuration cont ents for multiple vsc8244 devices (continued) 10-bit address contents (bits 7:0)
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 60 of 121 to write a value to a specific address of the eeprom, first read mii register bit 21e.11 and ensure that it is set. after confirming this bit is set, write the address to be written to mii register bits 21e.10:0, set mii register bit 21e.12 = 0, the 8-bit value to be written to mii register bits 22e.7:0, and then set mii register bit 21e.13 = 1. for successful read and write transactions always wait until 21e.11 = 1 before performing another eeprom read or write operation. figure 25. eeprom read and write register flow wait for ready 21e.11 = 0 21e.11 = 1 read or write 21e.10:0 = write address 21e.12 = 0 22e.7:0 = data to write write eeprom data 21e.10:0 = address to read 21e.12 = 1 21e.13 = 1 21e.13 = 1 wait for ready 21e.11 = 0 21e.11 = 1 read eeprom data read data = 22e.15:8 start
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 61 of 121 23 mii register set the mii register map quick reference is listed on the foll owing two pages:see ?cmode pin configuration? on page 52. note: for mii registers 16-31 and extended mii registers 16e-30e, any bits marked as ?reserved? should be processed as read only and their states as undefined. in writing to registers with these reserved bits, one must perform a technique known commonly as ?ready-modify write? where t he entire register is read and only the intended bits to be changed are modified. these reserved bits cannot be changed and their read state cannot be considered static or unchanging. table 32. mii register bit modes register bit type description s ?sticky? 1 - this bit will retain value after a software reset and if mii register 22.9 = 1 1 ?sticky? refers to the behavior of the register bit(s) after a software reset. if an ?s? appears in the sticky column, the corresponding bit(s) will retain their values after a software reset, as long as mii register bit register 22 (16h) ? extended control & status register is set. if an ?ss? appears in the sticky column, the corresponding bit(s) will retain their values after a software reset, regardless of the state of mii register bit register 22 (16h) ? extended control & status register . ss ?super sticky? 1 - this bit will retain va lue after a software reset r/w read/write bit ro read only bit wo write only bit sc self-clearing bit ll this bit will latch the bit on low. the bit self-clears on read lh this bit will latch the bit on high. the bit self-clears on read cmode defined by cmode pin settings
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 62 of 121 23.1 mii extended page registers in order to provide additional functionality beyond the ieee802 .3 specified 32 mii registers, the vsc8244 contains an extended paging mode that allows an additional 15 registers. access to the extended page registers (regi sters 16e - 30e) is enabled by writing a ?0001? to mii register 31. when extended page register access is enabled, read/writes to mii registers 16 through 30 will affect the extended mii registers 16e through 30e. mii regi sters 0 through 15 are not affected by the state of the extende d page register access. writing a ?0000? to mii register 31 will restore normal mii register access. figure 26. extended page register 0 1 2 3 . . . . . . . 15 16e 17e 18e 19e . . . . . . . 30e 16 17 18 19 . . . . . . . 30 0000 0001 31 normal page registers extended page registers
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 63 of 121 23.3 mii register quick reference table 33. mii register quick reference register1514131211109876543210 0 (00h) mode control software reset loopback 0 forced speed select[0] auto-neg enable 1 power- down isolate 0 restart auto-neg 0 duplex mode collision te s t forced speed select[1] reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 1 (01h) mode status 100b-t4 0 100b-x fdx 100b-x hdx 10b-t fdx 1 10b-t hdx 1 100b-t2 fdx 100b-t2 hdx extended status reserved 0 preamble suppressio n auto-neg complete 0 remote fault 0 auto-neg capability 1 link status 0 jabber detect 0 extended capability 1 2 (02h) phy identifier #1 oui_msb[ 3] oui_msb[ 4] oui_msb[ 5] oui_msb[ 6] oui_msb[ 7] oui_msb[ 8] oui_msb[ 9] oui_msb[ 10] oui_msb[ 11] oui_msb[ 12] oui_msb[ 13] oui_msb[ 14] oui_msb[ 15] oui_msb[ 16] oui_msb[ 17] oui_msb[ 18] 3 (03h) phy identifier #2 oui_lsb[1 9] oui_lsb[2 0] oui_lsb[2 1] oui_lsb[2 2] oui_lsb[2 3 oui_lsb[2 4] vendor model number[5] vendor model number[4] vendor model number[3] vendor model number[2] vendor model number[1] vendor model number[0] vendor rev number[3] vendor rev number[2] vendor rev number[1] vendor rev number[0] 4 (04h) auto-neg advertiseme nt next page 0 reserved 0 remote fault reserved 0 asymmetri c pause cmode symmetric pause cmode 100b-t4 0 100b-x fdx 100b-x hdx 10b-t fdx cmode 10b-t hdx cmode selector field[4] selector field[3] selector field[2] selector field[1] selector field[0] 5 (05h) auto-neg link partner ability next page 0 ack 0 remote fault reserved 0 asymmetri c pause 0 symmetric pause 0 100b-t4 0 100b-x fdx 100b-x hdx 10b-t fdx 0 10b-t hdx 0 selector field[4] selector field[3] selector field[2] selector field[1] selector field[0] 6 (06h) auto-neg expansion reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 parallel detect fault lp np able 0 np able 1 page received lp auto- neg able 0 7 (07h) auto-neg np transmit next page 0 reserved 0 message page ack2 0 toggle 0 message/ unformatte d[10] message/ unformatte d[9] message/ unformatte d[8] message/ unformatte d[7] message/ unformatte d[6] message/ unformatte d[5] message/ unformatte d[4] message/ unformatte d[3] message/ unformatte d[2] messag/ unformatte d[1] message/ unformatte d[0] 8 (08h) auto-neg link partner np receive lp next page lp ack 0 lp message page lp ack2 0 lp toggle 0 lp message/ unformatte d[10] lp message/ unformatte d[9] lp message/ unformatte d[8] lp message/ unformatte d[7] lp message/ unformatte d[6] lp message/ unformatte d[5] lp message/ unformatte d[4] lp message/ unformatte d[3] lp message/ unformatte d[2] lp message/ unformatte d[1] lp message/ unformatte d[0] 9 (09h) 1000base-t control transmit test[1] transmit te st [ 2 ] transmit test[3] m/s config enable 0 m/s config value 0 port type 1 1000b-t fdx 1000b-t hdx reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 10 (0ah) 1000base-t status m/s config fault m/s config resolution 1 local receiver status remote receiver status lp 1000b- t fdx 0 lp 1000b- t hdx 0 reserved 0 reserved 0 idle error count[7] 0 idle error count[6] 0 idle error count[5] 0 idle error count[4] 0 idle error count[3] 0 idle error count[2] 0 idle error count[1] 0 idle error count[0] 0 11 (0bh) reserved reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 12 (0ch) reserved reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 13 (0dh) reserved reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 14 (0eh) reserved reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 15 (0fh) 1000base-t status extension 1000b-x fdx 1000b-x hdx 1000b-t fdx 1000b-t hdx reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 reserved 0 16 (10h) 100base-tx status extension 100b-tx descrambl er locked 0 100b-tx lock error detected 100b-tx disconnect state 0 100b-tx current link status 0 100b-tx receive error detected 100b-tx transmit error detected 100b-tx ssd error detected 100b-tx esd error detected reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- 17 (11h) 1000base-t status extension 1000b-t descrambl er locked 0 1000b-t lock error detected 1000b-t disconnect state 0 1000b-t current link status 1000b-t receive error detected 1000b-t transmit error detected 1000b-t ssd error detected 1000b-t esd error detected 1000b-t carrier extension error non- compliant bcm5400 detected reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- 18 (12h) bypass control transmit disable 0 reserved -- reserved -- reserved -- reserved -- reserved -- reserved 0 1000bt transmitter test clock enable reserved -- reserved -- disable automatic pair swap correction disable polarity correction parallel- detect control reserved -- disable auto 1000b-t np 125mhz clock output enable 19 (13h) reserved reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- 20 (14h) reserved reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- 21 (15h) reserved reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- 22 (16h) extended control & status link disable jabber detect disable 10b-t/ 100b-tx echo disable reserved -- squelch[1] 0 squelch[0] 0 sticky reset enable eof error detected 0 10b-t disconnect 0 10b-t link status 0 reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- 23 (17h) extended phy control #1 reserved -- mac i/f mode[2] 0 mac i/f mode[1] 0 mac i/f mode[0] 0 rgmii tx_clk skew seletction rgmii tx_clk skew seletction rgmii rx_clk skew seletction rgmii rx_clk skew seletction reserved -- reserved -- rx idle clock enable reserved -- far end loopback mode enable mac/ media mode select mac/ media mode select eeprom status
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 64 of 121 24 (18h) extended phy control #2 100/ 1000b-tx edge rate[2] 100/ 1000b-tx edge rate[1] 100/ 1000b-tx edge rate[0] enable picmg 2.16 miser mode reserved -- reserved -- tx fifo depth[2] (rgmii) 1 tx fifo depth[1] (rgmii) 0 tx fifo depth[0] (rgmii) 0 rx fifo depth[2] (rtbi) rx fifo depth[1] (rtbi) rx fifo depth[0] (rtbi) reserved -- reserved -- reserved -- 1000bt connector loopback 0 25 (19h) interrupt mask interrupt pin enable 0 speed state- change interrupt link state- change interrupt mask duplex state- change interrupt auto-neg error interrupt mask auto-neg- done interrupt mask in-line powered device detected symbol error interrupt mask descrambl er lock- lost interrupt tx fifo interrupt mask rx fifo interrupt mask reserved -- false carrier interrupt mask cable impaired- detect interrupt master/ slave interrupt mask rx_er interrupt mask 26 (1ah) interrupt status interrupt status speed state- change interrupt link state- change interrupt status fdx state- change interrupt status auto-neg error interrupt status auto-neg- done interrupt status in-line powered device interrupt symbol error interrupt status descrambl er lock- lost interrupt tx fifo interrupt status rx fifo interrupt status reserved -- false carrier interrupt status cable impaired- detect interrupt master/ slave interrupt status rx_er interrupt status 27 (1bh) serial led control led pin 4 config cmode led pin 4 config cmode led pin 3 config cmode led pin 3 config cmode led pin 2 config cmode led pin 2 config cmode led pin 1 config cmode led pin 1 config cmode led pin 0 config cmode led pin 0 config cmode led pulse- stretch rate/blink rate led pulse- stretch rate/blink rate led pulse- stretch/ blink select led pulsing behavior led link/ activity behavior led duplex/ collision behavior 28 (1ch) auxiliary control & status auto-neg complete 0 auto-neg disabled 0 mdi/mdi-x xover indication cd pair swap a polarity inversion 0 b polarity inversion 0 c polarity inversion 0 d polarity inversion 0 reserved -- enhanced actiphy enable fdx status 0 speed status[1] speed status[0] reserved -- actiphy sleep timer actiphy sleep timer 29 (1dh) reserved reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- 3-- (1eh) reserved reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- 31 (1fh) extended page acess reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- extended page access key: bit name (read/ writable) bit name (read only) table 33. mii register quick reference (continued) register1514131211109876543210
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 65 of 121 23.4 mii register quick reference - extended page mode table 34. mii register quick reference - extended page mode register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16e (10h) remote fault control & status reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- 17e (11h) clk125 micro clock reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- clk125mi cro enable 18e (12h) reserved reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- 19e (13h) reserved reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- 20e (14h) extended phy control #3 reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- clk125mi cro frequency reserved -- reserved -- reserved -- enable link speed auto- link speed auto- downshift link speed auto- downshift link speed auto- downshift reserved -- 21e (15h) eeprom status & control reserved -- re-read eeprom on software eeprom access enable eeprom read/ write eeprom ready 1 eeprom address 0 eeprom address 0 eeprom address 0 eeprom address 0 eeprom address 0 eeprom address 0 eeprom address 0 eeprom address 0 eeprom address 0 eeprom address 0 eeprom address 0 22e (16h) eeprom data read/write eeprom read data 0 eeprom read data 0 eeprom read data 0 eeprom read data 0 eeprom read data 0 eeprom read data 0 eeprom read data 0 eeprom read data 0 eeprom write data 0 eeprom write data 0 eeprom write data 0 eeprom write data 0 eeprom write data 0 eeprom write data 0 eeprom write data 0 eeprom write data 0 23e (17h) extended phy control #4 phy address phy address phy address phy address phy address enable device detection device detection status device detection status crc counter crc counter crc counter crc counter crc counter crc counter crc counter crc counter 24e (18h) reserved reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- 25e (19h) reserved reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- 26e (1ah) reserved reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- 27e (1bh) reserved reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- 28e (1ch) reserved reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- reserved -- 29e (1dh) 1000base-t epg #1 epg enable epg run/ stop transmissi on duration packet length packet length inter- packet gap destinatio n address 0 destinatio n address 0 destinatio n address 0 destinatio n address 1 source address source address source address source address reserved -- bad fcs generatio n 30e (1eh) 1000base-t epg #2 epg packet payload epg packet payload epg packet payload epg packet payload epg packet payload epg packet payload epg packet payload epg packet payload epg packet payload epg packet payload epg packet payload epg packet payload epg packet payload epg packet payload epg packet payload epg packet payload key: bit name (read/ writable) bit name (read only)
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 66 of 121 24 mii register descriptions registers 0-15 comply with the ieee 802. 3 standard. enhancem ents beyond the specification ar e noted within each of these registers. for more information on normal operation of registers 0-15, pl ease consult with the ieee standard. 24.1 register 0 (00h) ? mode control register register 0 (00h) ? mode control register bit name access states reset value 15 software reset 1 1 a soft reset restores all smi registers to their default states, except for registers marked with an ?s? or ?ss? in the sticky column. after setting this bit, the user needs to wait 4 microseconds to initiate the next smi access. r/w sc 1 = reset asserted 0 = reset de-asserted 0 14 loopback 2 2 the loopback mechanism works in the current speed and duplex mode of operation. if the link is down the operating mode is deter mined by bits 0.13 and 0.6 (forced speed selection) and 0.8. r/w 1 = loopback on 0 = loopback off 0 6, 13 forced speed selection r/w 00 = 10mbps 01 = 100mbps 10 = 1000mbps 11 = reserved 10 12 auto-negotiation enable r/w 1 = auto-negotiation enabled 0 = auto-negotiation disabled 1 11 power-down r/w 1 = power-down 0 = power-up 0 10 isolate r/w 1 = disable rgmii/rtbi outputs 0 = normal operation 0 9 restart auto-negotiation r/w sc 1 = restart mii 0 = normal operation 0 8 duplex mode r/w 1 = full duplex 0 = half duplex 0 7 collision test enable r/w 1 = collision test enabled 0 = collision test disabled 0 6 msb for speed selection (see bit 13 above) - - 1 5:0 reserved - - 000000
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 67 of 121 24.2 register 1 (01h) ? mode status register 24.3 register 2 (02h) ? phy identifier register #1 24.4 register 3 (03h) ? phy identifier register #2 register 1 (01h) ? mode status register bit name access states reset value 15 100base-t4 capability ro 1 = 100base-t4 capable 0 14 100base-tx fdx capability ro 1 = 100base-tx fdx capable 1 13 100base-tx hdx capability ro 1 = 100base-tx hdx capable 1 12 10base-t fdx capability ro 1 = 10base-t fdx capable 1 11 10base-t hdx capability ro 1 = 10base-t hdx capable 1 10 100base-t2 fdx capability ro 1 = 100base-t2 fdx capable 0 9 100base-t2 hdx capability ro 1 = 100base-t2 hdx capable 0 8 extended status enable ro 1 = extended status information present in r15 1 7 reserved ro 0 6 preamble suppression capability ro 1 = mf preamble may be suppressed 0 = mf preamble always required 1 5 auto-negotiation complete ro 1 = auto-negotiation complete 0 = auto-negotiation not complete 0 4 remote fault ro lh 1 = far-end fault detected 0 = no fault detected 0 3 auto-negotiation capability ro 1 = auto-negotiation capable 1 2 link status 1 1 if link status bit is equal to ?1? and power down is subsequently set (mii register 0.11 = 1), link status bit may not clear. to clear the bit in this scenario, write mii register 0.11 = 1, then mii register 0.11 = 0, and finally mii r egister 0.11 = 1. this will ensure the link status bit is clear ed when powerdown is enabled. ro ll 1 = link is up 0 = link is down 0 1 jabber detect ro lh 1 = jabber condition detected 0 = no jabber condition detected 0 0 extended capability ro 1 = extended register capable 1 register 2 (02h) ? phy identifier register #1 bit name access states reset value 15:0 organizationally unique identifier ro oui most significant bits (vitesse oui bits 3:18) 0000000000001111 or (000fh) register 3 (03h) ? phy identifier register #2 bit name access states reset value 15:10 organizationally unique identifier ro oui least significant bits (vitesse oui bits 19:24) 110001 9:4 vendor model number ro vendor?s model number (ic) 101100 = vsc8244 3:0 vendor revision number ro vendor?s revision number (ic) 0010 = silicon revision c
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 68 of 121 24.5 register 4 (04h) ? auto-negotiation advertisement register 24.6 register 5 (05h) ? auto-negotiation link partner ability register 24.7 register 6 (06h) ? auto-negotiation expansion register register 4 (04h) ? auto-negotiation advertisement register bit name access states reset value 15 next-page transmission request r/w 1 = next-page transmission request 0 14 reserved ro 0 13 transmit remote fault r/w 1 = transmit remote fault 0 12 reserved technologies r/w 0 11 advertise asymmetric pause r/w 1 = advertise asymmetric pause capable cmode 10 advertise symmetric pause r/w 1 = advertise symmetric pause capable cmode 9 advertise 100base-t4 capability r/w 1 = 100base-t4 capable 0 8 advertise 100base-tx fdx r/w 1 = 100base-tx fdx capable cmode 7 advertise 100base-tx hdx r/w 1 = 100base-tx hdx capable cmode 6 advertise 10base-t fdx r/w 1 = 10base-t fdx capable cmode 5 advertise 10base-t hdx r/w 1 = 10base-t hdx capable cmode 4:0 advertise selector field r/w 00001 register 5 (05h) ? auto-negotiation link partner ability register bit name access states reset value 15 lp next-page transmit request ro 1 = lp np transmit request 0 14 lp acknowledge ro 1 = lp acknowledge 0 13 lp remote fault ro 1 = lp remote fault 0 12 reserved ro - 0 11 lp asymmetric pause capability ro 1 = lp advertise asymmetric pause capable 0 10 lp symmetric pause capability ro 1 = lp advertise symmetric pause capable 0 9 lp advertise 100base-t4 capa- bility ro 1 = lp advertise 100base-t4 capable 0 8 lp advertise 100base-tx fdx ro 1 = lp 100base-tx fdx capable 0 7 lp advertise 100base-tx hdx ro 1 = lp 100base-tx hdx capable 0 6 lp advertise 10base-t fdx ro 1 = lp 10base-t fdx capable 0 5 lp advertise 10base-t hdx ro 1 = lp 10base-t hdx capable 0 4:0 lp advertise selector field ro lp advertise selector field 00000 register 6 (06h) ? auto-negotiation expansion register bit name access states reset value 15:5 reserved ro 00000000000 4 parallel detection fault ro lh 1 = parallel detection fault 0 3 lp next-page able ro 1 = lp next-page capable 0 2 local phy next-page able ro 1 = next-page capable 1 1 page received ro lh 1 = new page has been received 0 0 lp auto-negotiation able ro 1 = lp auto-negotiation capable 0
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 69 of 121 24.8 register 7 (07h) ? auto-negotiation next-page transmit register 24.9 register 8 (08h) ? auto-negotiation link partner next-page receive register register 7 (07h) ? auto-negotiation next-page transmit register bit name access states reset value 15 next page r/w 1 = more pages follow 0 = last page 0 14 reserved ro 0 13 message page r/w 1 = message page 0 = unformatted page 1 12 acknowledge2 r/w 1 = will comply with request 0 = cannot comply with request 0 11 to g g l e ro 1 = previous transmitted lcw == 0 0 = previous transmitted lcw == 1 0 10:0 message/unformatted code r/w 00000000001 register 8 (08h) ? auto-negotiation link partner next-page receive register bit name access states reset value 15 lp next page ro 1 = more pages follow 0 = last page 0 14 lp acknowledge ro 1 = lp acknowledge 0 13 lp message page ro 1 = message page 0 = unformatted page 0 12 lp acknowledge2 ro 1 = lp will comply with request 0 11 lp toggle ro 1 = previous transmitted lcw == 0 0 = previous transmitted lcw == 1 0 10:0 lp message/unformatted code ro 00000000000
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 70 of 121 24.10 register 9 (09h) ? 1000base-t control register 9.15:13 transmitter/receiver test mode this test is valid only in 1000base-t mode. refer to ieee 802.3-2002, secti on 40.6.1.1.2 for more information. ? test mode 1: the phy repeatedly transmits the following sequence of data symbols from all four transmitters: {{"+2" followed by 127 "0" symbols}, {"-2" followed by 127 "0" symbols}, {"+1" followed by 127 "0" symbols}, {"-1" followed by 127 "0" symbols}, {128 "+2" symbols, 128 "-2" symbols, 128 "+ 2" symbols, 128 "-2" symbols}, {1024 "0" symbols}}. the transmitter should use a 125.00 mhz 0.01% clo ck and should operate in master timing mode. ? test mode 2: the phy transmits the data symbol sequence {+2, -2} repeatedly on all channels. the transmitter should use a 125.00 mhz 0.01% clock in the master timing mode. ? test mode 3: the phy transmits the data symbol sequence {+2, -2} repeatedly on all channels. the transmitter should use a 125.00 mhz 0.01% clock and should operate in slave timing mode. register 9 (09h) ? 1000base-t control register bit name access states reset value 15:13 transmitter test mode r/w described below, per i eee 802.3, 40.6.1.1.2 000 12 master/slave manual configu- ration enable r/w 1 = enable master/slave manual configura- tion value 0 = disable master/slave manual configura- tion value 0 11 master/slave manual configu- ration value r/w 1 = configure phy as master during mas- ter/slave negotiation, only when bit 9.12 is set to logical one. 0 = configure phy as slave during master/ slave negotiation, only when bit 9.12 is set to logical one. 0 10 port type r/w 1 = multi-port device 0 = single-port device 1 9 1000base-t fdx capability r/w 1 = phy is 1000base-t fdx capable cmode 8 1000base-t hdx capability r/w 1 = phy is 1000base-t hdx capable cmode 7:0 reserved r/w 00000000 table 35. transmitter/receiver test mode bit 1 (9.15) bit 2 (9.14) bit 3 (9.13) test mode 0 0 0 normal operation 0 0 1 test mode 1 ? transmit waveform test 010 test mode 2 ? transmit jitter test in master mode 011 test mode 3 ? transmit jitter test in slave mode 1 0 0 test mode 4 ? transmitter distortion test 1 0 1 reserved; operation not defined 1 1 0 reserved; operation not defined 1 1 1 reserved; operation not defined
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 71 of 121 ? test mode 4: the phy transmits the sequence of symbols generated by the following scrambler generator polynomial, bit generation, and level mappings: the maximum-length shift register used to generate the sequenc es defined by this polynomial is updated once per symbol interval (8ns). the bits stored in the shift register delay line at a particular time n are denoted by scrn[10:0]. at each symbol period, the shift register is advanced by one bit, and one new bit represented by scrn[0] is generated. bits scr n [8] and scr n [10] are exclusive-or'd together to generate the next scr n [0] bit. the bit sequences, x0 n , x1 n , and x2 n , generated from combinations of the scrambler bits as shown in the following equations, shall be used to generate the quinary symbols, s n , as shown in the following table. the transmitter should use a 125.00 mhz 0.01% clock and should operate in master timing mode. table 36. test mode 4 x2 n x1 n x0 n quinary symbol, s n 000 0 001 1 010 2 011 -1 100 0 101 1 110 -2 111 -1
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 72 of 121 24.11 register 10 (0ah) ? 1000base-t status register 24.12 register 11 (0bh) ? reserved register 24.13 register 12 (0ch) ? reserved register 24.14 register 13 (0dh) ? reserved register register 10 (0ah) ? 1000base-t status register bit name access states reset value 15 master/slave configuration fault ro lh sc 1 = master/slave configuration fault detected 0 = no master/slave configuration fault detected 0 14 master/slave configuration resolution ro 1 = local phy configuration resolved to mas- ter 0 = local phy configuration resolved to slave 1 13 local receiver status ro 1 = local receiver ok (loc_rcvr_status == ok) 0 = local receiver not ok (loc_rcvr_status == not_ok) 0 12 remote receiver status ro 1 = remote receiver ok (rem_rcvr_status == ok) 0 = remote receiver not ok (rem_rcvr_status == not_ok) 0 11 lp 1000base-t fd x capability ro 1 = lp 1000base-t fdx capable 0 = lp not 1000base-t fdx capable 0 10 lp 1000base-t hdx capability ro 1 = lp is 1000base-t hdx capable 0 = lp is not 1000base-t hdx capable 0 9:8 reserved ro 00 7:0 idle error count ro sc 00000000 register 11 (0bh) ? reserved register bit name access states reset value 15:0 reserved ro 00000000 00000000 register 12 (0ch) ? reserved register bit name access states reset value 15:0 reserved ro 00000000 00000000 register 13 (0dh) ? reserved register bit name access states reset value 15:0 reserved ro 00000000 00000000
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 73 of 121 24.15 register 14 (0eh) ? reserved register 24.16 register 15 (0fh) ? 1000base-t status extension register #1 register 14 (0eh) ? reserved register bit name access states reset value 15:0 reserved ro 00000000 00000000 register 15 (0fh) ? 1000base-t status extension register #1 bit name access states reset value 15 1000base-x fdx capability ro 1 = phy is 1000base-x fdx capable 0 = phy is not 1000base-x fdx capable 0 14 1000base-x hdx capability ro 1 = phy is 1000base-x hdx capable 0 = phy is not 1000base-x hdx capable 0 13 1000base-t fdx capability ro 1 = phy is 1000base-t fdx capable 0 = phy is not 1000base-t fdx capable 1 12 1000base-t hdx capability ro 1 = phy is 1000base-t hdx capable 0 = phy is not 1000base-t hdx capable 1 11:0 reserved ro 000000000000
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 74 of 121 24.17 register 16 (10h) ? 100base-tx status extension register 24.18 register 17 (11h) ? 1000base-t status extension register #2 register 16 (10h) ? 100base-tx status extension register bit name access states reset value sticky 15 100base-tx descrambler locked ro 1 = descrambler locked 0 = descrambler not locked 0 14 100base-tx lock error detected ro lh 1 = lock error detected since last read 0 = lock error not detected since last read 0 13 100base-tx disconnect state ro lh 1 = phy 100base-tx link disconnected 0 = phy 100base-tx link not disconnected 0 12 100base-tx current link status ro 1 = phy 100base-tx link active 0 = phy 100base-tx link inactive 0 11 100base-tx receive error detected ro lh 1 = receive error detected since last read 0 = receive error not detected since last read 0 10 100base-tx transmit error detected ro lh 1 = transmit error detected since last read 0 = transmit error not detected since last read 0 9 100base-tx ssd (start-of-stream delimiter) error detected ro lh 1 = ssd error detected since last read 0 = ssd error not detected since last read 0 8 100base-tx esd (end-of-stream delimiter) error detected ro lh 1 = esd error detected since last read 0 = esd error not detected since last read 0 7:0 reserved ro -- register 17 (11h) ? 1000base-t status extension register #2 bit name access states reset value sticky 15 1000base-t descrambler locked ro 1 = descrambler locked 0 = descrambler not locked 0 14 1000base-t lock error detected ro lh 1 = lock error detected since last read 0 = lock error not detected since last read 0 13 1000base-t disconnect state ro lh 1 = phy 1000base-t link disconnected 0 = phy 1000base-t link not disconnected 0 12 1000base-t current link status ro 1 = phy 1000base-t link active 0 = phy 1000base-t link inactive 0 11 1000base-t receive error detected ro lh 1 = receive error detected since last read 0 = receive error not detected since last read 0 10 1000base-t transmit error detected ro lh 1 = transmit error detected since last read 0 = transmit error not detected since last read 0 9 1000base-t ssd (start-of-stream delimiter) error detected ro lh 1 = ssd error detected since last read 0 = ssd error not detected since last read 0 8 1000base-t esd (end-of-stream delimiter error) error detected ro lh 1 = esd error detected since last read 0 = esd error not detected since last read 0 7 1000base-t carrier extension error detected ro lh 1 = carrier extension error detected since last read 0 = carrier extension error not detected since last read 0 6 non-compliant bcm5400 detected ro 1 = non-compliant bcm5400 detected 0 = non-compliant bcm5400 not detected 0 5:0 reserved ro --
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 75 of 121 24.19 register 18 (12h) ? bypass control register 18.15 ? transmit disable when bit 18.15 is set to ?1?, t he analog blocks are powered down and zeros are s ent to the dac. decoder can by bypassed, receiving symbols through the 4-d s licer instead. in 100base-tx mode, to pass the unaligned symbols directly to the mii interface, this control bit sh ould be set only when the 4b5b decoder is also bypassed. 18.8 ? 1000bt transmitter test clock enable when bit 18.8 is written to a ?1?, the clk125 micro output pin becomes a test pin for the transmit clock ?tx_tclk? of a particular phy port. this capability is intended to enable measurement of transmitter timing jitter, as specified in ieee standard 802.3- 2002, section 40.6.1.2.5. when in ieee-specified tran smitter test modes 2 or 3 (see ieee 802.3-2002, secti on 40.6.1.1.2 and mii register bits 9.15:13), the peak-to-peak jitter of the zero-crossings of the differential signal output at the mdi, relativ e to the corresponding edge of tx_tclk, is measured. the corresponding edge of tx_tclk is the edge of the transmit test clock, in polarity and time, that generates the zero-crossing transition being measured. while transmitter test mode clocks tx_tclk_n are intended only for characterization test purposes, clk125 micro is intended, for example, to serve as a general purpose system or mac reference clock. five distinct clock signals can be multiplexed onto the vsc8244?s clk125 micro pin, depending on a combination of the settings of mii register bits 9.15:13, mii register bit 18.8, and mii register bit 18.0 (clk125 output enable), as specified in the following table: register 18 (12h) ? bypass control register bit name access states reset value sticky 15 transmit disable r/w 1 = transmitter disabled in phy 0 = transmitter enabled 0 14:9 reserved ro -- 8 1000bt transmitter test clock enable r/w 1 = enable tx_tclk test output on clk125 micro pin 0 = disable tx_tclk test output on clk125 micro pin 0 7:6 reserved ro -- 5 disable automatic pair swap cor- rection r/w 1 = disable pair swap correction 0 = enable pair swap correction 0 s 4 disable polarity correction r/w 1 = disable polarity inversion correction 0 = enable polarity inversion correction 0 s 3 parallel-detect control r/w 1 = do not ignore advertised ability 0 = ignore advertised ability 1 s 2 reserved ro -- 1 disable automatic 1000base-t next-page exchange r/w 1 = disable automatic 1000base-t next-page exchanges 0 = enable automatic 1000base-t next-page exchanges 0 s 0 125mhz mac clock output enable r/w 1 = enable 125mhz output clock pin clk125 mac 0 = disable 125mhz output clock pin clk125 mac 1 s
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 76 of 121 18.5 ? disable automatic pair swap correction 1 when bit 18.5 is set to ?0?, the phy automatically corrects pair swaps between subchannels a and b, and between subchannels c and d, due to ?mdi/mdi-x crossover?. it will also correct pair swaps between subchannels c and d due to cabling errors. when bit 18.5 is set to ?1?, the phy does not correct pair swaps. 18.4 ? disable polarity correction 1 when bit 18.4 is set to ?0?, the phy automatically corrects pola rity inversion on all the subchannels. when bit 18.4 is set to ?1?, the phy does not compensate for polarity inversions. 18.3 ? parallel-detect control when bit 18.3 is ?1?, mii register 4, bits [8:5], are taken in to account when attempting to parallel-detect. this is the defaul t behavior expected by the standard. setting 18.3 to a ?0? will result in auto-negotiation ignoring the advertised abilities, as specified in mii register 4, during parallel detection of a non-auto-negotiating 10base-t or 100base-tx phy. 18.2 ? disable pulse shaping filter 1 when bit 18.2 is set to ?1?, the 1000base-t tw o-tap digital transmit filter is disabled. 18.1 ? disable automatic 1000base-t next-page exchanges bit 18.1 is used to control the automatic exchange of 1000 base-t next-pages defined in ieee 802.3-2002 (annex 40c). when this bit is set, the automatic exchange of these pages is disabled, and the control is returned to the user through the smi aft er the base page has been exchanged. the user then has complete responsibility to: ? send the correct sequence of next-pages to the link partner, and ? determine common capabilities and force the device into the correct configuration following successful exchange of pages. when bit 18.1 is reset to ?0?, the 1000base-t related next-page s are automatically exchanged without user intervention. if the next page bit 4.15 was set by the user in the auto-negotiation advertisement register at the time the auto-negotiation was restarted, control is returned to the user for additional next-pages following the 1000base-t next-page exchange. if both 18.1 and 4.15 are reset when an auto-negotiation sequence is initiated, all next-page exchange is automatic, including sourcing of null pages. no user notification is provided until either auto-negotiation completes or fails. see the description of register bit 4.15 for more details on standard next-page exchanges. table 37. transmitter test clock enable signal multiplexed onto clk125 pin enabled by mii register states tx_tclk_0 phy0, ((9.15:13 == 010) || (9.15:13 == 011) || (18.8 ==1)) tx_tclk_1 phy1, ((9.15:13 == 010) || (9.15:13 == 011) || (18.8 ==1)) tx_tclk_2 phy2. ((9.15:13 == 010) || (9.15:13 == 011) || (18.8 ==1)) tx_tclk_3 phy3, ((9.15:13 == 010) || (9.15:13 == 011) || (18.8 ==1)) clk125 1 1 only phy port 0?s bit 18.0 controls the operation of clk125 (see section 24.19: "register 18 (12h) ? bypass control register" ). phy0, 18.0 == 1 1 this bit applies only in 1000base-t mode
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 77 of 121 18.0 ? enable 125mhz mac free-running clock output when bit 18.0 is set to ?1?, the vsc8244 provides a free-running, general-purpose 125mhz clock on the clk125 mac output pin. the electrical specifications for this clock corresponds to the current setting for vddio mac . this clock can be used by a mac, a switch, or other synchronous logic. by default, this pin is enabled, which enables the clock output, independent of the status of any link, unless a hardware reset is active (which also powers down the pll). when disabled, this pin is normally driven low. note that only phy port 0?s bit 18.0 controls the operation of clk125 mac . 24.20 register 19 (13h) ? reserved 24.21 register 20 (14h) ? reserved 24.22 register 21 (15h) ? reserved register 19 (13h) ? reserved bit name access states reset value sticky 15:0 reserved ro -- register 20 (14h) ? reserved bit name access states reset value sticky 15:0 reserved ro -- register 21 (15h) ? reserved bit name access states reset value sticky 15:0 reserved ro --
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 78 of 121 24.23 register 22 (16h) ? extended control & status register 22.15 ? force 10bt link high when bit 22.15 is set to ?0?, the vsc8244 link integrity state machine runs automatically; it also controls link pass status. w hen bit 22.15 is set to ?1?, the link integrity state machine is bypassed, and the phy is forced into link pass status. 22.14 ? disable jabber detect when bit 22.14 is set to ?0?, the vsc8244 automatically shuts off the transmitter when a transmission request exceeds the ieee-specified time limit. when bit 22.14 is set to ?1?, transmission requests are allo wed to be arbitraril y long without shutt ing down the transmitter. 22.13 ? disable 10base-t echo mode when bit 22.13 is set to ?1?, the logica l state of the tx_en pin will not echo onto the crs pin, effectively disabling crs from being asserted in half-duplex operation. when bit 22.13 is set to ?0?, the tx_en pin will be echoed onto the crs pin. data on txd is echoed to rxd in 10base-t mode only. 22.11:10 ? squelch control when bits 22.11:10 are set to ?00?, th e vsc8244 uses the squelch threshold le vels prescribed by the ieee?s 10base-t specification. when bits 22.11:10 are set to ?01?, the squel ch level is decreased, which may improve the bit error rate performance on long loops. when bits 22.11:10 are set to ?10?, t he squelch level is increased, which may improve the bit error rate in high-noise environments. register 22 (16h) ? extended control & status register bit name access states reset value sticky 15 force 10bt link high r/w 1 = disable link integrity test 0 = enable link integrity test 0 s 14 jabber detect disable r/w 1 = disable jabber detect 0 = enable jabber detect 0 s 13 disable 10base-t echo r/w 1 = disable 10base-t echo 0 = enable 10base-t echo 1 s 12 reserved ro - -- 11:10 10base-t squelch control r/w 00 = normal squelch 01 = low squelch 10 = high squelch 11 = reserved 00 s 9 sticky reset enable r/w 1 = all bits marked as sticky will retain their values during software reset 0 = all bits marked as sticky will be changed to default values during software reset 1 ss 8 eof error detected ro sc 1 = eof error detected since last read 0 = eof error not detected since last read 0 7 10base-t disconnect state ro sc 1 = 10base-t link disconnected 0 = 10base-t link connected 0 6 10base-t link status ro 1 = 10base-t link active 0 = 10base-t link inactive 0 5:0 reserved ro - --
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 79 of 121 22.9 - sticky reset enable when bit 22.9 is set, all mii re gister bits that are marked with an ?s? in th e ?sticky? column will reta in their values during a software reset. when cleared, all mii register bits that are mark ed with an ?s? in the ?sticky? column will be changed to their default values during a software reset. note that bits marked wi th an ?ss? retain their values across software reset regardless of the setting of bit 22.9. 22.8 ? eof error when bit 22.8 returns a ?1?, a defective eof (end-of-frame) se quence has been received since the last time this bit was read. this bit is automatically set to ?0? when it is read. 22.7 ? 10base-t disconnect state bit 22.7 is set to ?1? if the 10base-t conn ection has been broken by the ca rrier integrity monitor sinc e the last read of this bit; otherwise, this bit is set to ?0?. 24.24 register 23 (17h) ? extended phy control register #1 register 23 (17h) ? extended phy control register #1 bit name access states reset value sticky 15 reserved ro always set to 0 -- 14:12 mac/media interface mode select r/w see table in register description below cmode ss 11:10 rgmii tx_clk skew selection r/w 00 = no skew on tx_clk 01 = 1.5ns skew on tx_clk 10 = 2ns skew on tx_clk 11 = 2.5ns skew on tx_clk cmode s 9:8 rgmii rx_clk skew selection r/w 00 = no skew on rx_clk 01 = 1.5ns skew on rx_clk 10 = 2ns skew on rx_clk 11 = 2.5ns skew on rx_clk cmode s 7:6 reserved ro - -- 5 rx idle clock enable r/w 1 = 25mhz clock on rx_clk pin enabled in act- iphy mode 0 = 25mhz clock on rx_clk pin disabled in act- iphy mode 1 ss 4 reserved ro -- 3 far end loopback mode enable r/w 1 = far end loopback is enabled 0 = far end loopback is disabled 0 2:1 mac/media interface mode select r/w see table in register description below cmode ss 0 eeprom status ro 1 = eeprom is detected on eeprom interface 0 = eeprom is not detec ted on eeprom inter- face 0
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 80 of 121 23.14:12, 2:1? mac/media interface mode select bits 23.14:12 and 23.2:1 are used to select the mac interface modes and the media interface modes. important: to change operating modes, write bits 14:12 and 2:1 to t heir intended settings. write a 1 to register bit 0:15 for the change to take effect. this sequence should be completed firs t, before all other configuration writes to other registers ar e perfomed. the reset value for these bits is dependent upon the state of the mac interface bits in the cmode hardware configuration. all combinations of these bits not indicated below are reserved: 23.11:10 ? rgmii tx_clk skew selection bits 23.11:10 specify the amount of clock delay added to the tx_clk line inside the vsc8244 in rgmii and rtbi interfaces. by enabling this internal delay, a pcb ?trombone? delay is not r equired as specified by the rgmii standard. multiple values are provided to compensate for pcb trace skews. the default values of these bits are specified by the rgmii skew bits in the cmode hardware configuration. 23.9:8 ? rgmii rx_clk skew selection bits 23.9:8 specify the amount of clock delay added to the rx_clk line inside the vsc8244 in rgmii and rtbi interfaces. by enabling this internal delay, a pcb ?trombone? delay is not r equired as specified by the rgmii standard. multiple values are provided to compensate for pcb trace skews. the default values of these bits are specified by the rgmii skew bits in the cmode hardware configuration. 23.5 ? rx idle clock enable when bit 23.5 is set to ?1?, a 25mhz clock is enabled on the rx_clk pin when the vsc8244 is in actiphy mode. when bit 23.5 is cleared, the rx_clk pin remains low during actiphy mode. this clock is enabled by default. 23.3 ? far end loopback mode enable when bit 23.3 is set to ?1?, all incoming data from the link partner on the current media interface is retransmitted back to th e link partner on the media interface. in addition the incoming data will also appear on the rx pins of the mac interface. any data present on the tx pins of the mac interface is ignored by the vsc8 244 when bit 23.3 is set. in order to avoid loss of data, bit 23.3 should not be set while the vsc8244 is receiving data on the media interface. bit 23.3 applies to all mac interfaces and t o all media interfaces in the vsc8244. when bit 23.3 is cleared, the vsc8244 resumes normal operation. this bit is cleared by default. table 38. mac/media interface mode select bits 23.14:12 bits 23.2:1 cmode mac inter- face [2:1] mac interface media interface options 001 10 11 rgmii cat-5 101 00 - rtbi cat-5 clause 37 autonegotiation disabled 100 01 00 rtbi cat-5 clause 37 autonegotiation enabled 100 10 - rtbi cat-5 clause 37 autonegotiation enabled - media converter 100 11 - rtbi cat-5 clause 37 autonegotiation enabled - interlock disabled 100 00 - rtbi cat-5 clause 37 autonegotiation autosense
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 81 of 121 23.0 ? eeprom status when bit 23.0 is set to ?1?, an eeprom has been detected on th e external eeprom interface. when cleared, bit 23.0 indicates that no eeprom has been detected. 24.25 register 24 (18h) ? extended phy control register #2 24.15:13 ? 100/1000base-t edge rate control bits 24.15:13 control the transmit dac slew rate in 100base-tx and 1000base-t modes only, as shown above. the difference between each setting is approximately 200ps to 300ps, with the ?+3? setting resulting in the slowest edge rate, and the ?-4? setting resulting in the fastest edge rate. 24.12 - enable picmg reduced power mode setting bit 24.12 turns off some portions of the phy's dsp block and reduces the phy's operating power. the dsp performance characteristics in this mode ar e configured to support the channel characteristics specified in the picmg 2.16 and picmg 3.0 specifications. see www.picmg.org for more information. this bit can be set in order to reduce power consumption in applications where the signal to noise ratio on the media is hi gh, such as ethernet over the backplane, or where the cable length is short (<10m). picmg reduced power mode may be used in certain applications with capacitively coupled media, rather than transformer coupled, to reduce pcb area and cost. refer to vitesse application note: transformerless ethernet concept and applications for more information. register 24 (18h) ? extended phy control register #2 bit name access states reset value sticky 15:13 100/1000base-t edge rate con- trol r/w 011 = +3 edge rate (slowest) 010 = +2 edge rate 001 = +1 edge rate 000 = nominal edge rate 111 = -1 edge rate 110 = -2 edge rate 101 = -3 edge rate 100 = -4 edge rate (fastest) 000 s 12 enable picmg reduced power mode r/w 1 = picmg reduced power mode is enabled 0 = picmg reduced power mode is disabled 0 s 11:10 reserved ro - -- 9:7 1000bt tx fifo depth control for rgmii r/w 000 = 5 symbols 001 = 4 symbols 010 = 3 symbols 011 = 2 symbols 100 = 1 symbol 101 to 111 = reserved 100 s 6:4 1000bt rx fifo depth control for rtbi r/w 000 = 5 symbols 001 = 4 symbols 010 = 3 symbols 011 = 2 symbols 100 = 1 symbol 101 to 111 = reserved 100 s 3:1 reserved ro - -- 0 1000bt connector loopback r/w 1 = active (see section 21.5: "connector loop- back" for more information) 0 = disabled 0
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 82 of 121 24.9:7 ? 1000bt tx fifo depth control for rgmii bits 24.9:7 control symbol buffering for the transmit synchronization fifo used in all 1000bt modes. an internal fifo is used t o synchronize the clock domains be tween the mac transmit clock and the phy?s clo ck (e.g., refclk), used to transmit symbols on the local phy?s twisted pair interface. the ieee mode supports up to 1518-byte packet size with the minimum inter-packet gap (ipg). the jumbo packet mode adds latency to the path to support up to 9600-byte packets with the minimum inter-packet gap (ipg). when using jumbo packet mode, a larger ipg is recommended due to the possible compression of the ipg at the output of the fifo. 24.6:4 ? 1000bt rx fifo depth control for rtbi used in 1000bt rtbi modes only, bits 24.6:4 control symbol buffering as determined by the receive synchronization fifo. an internal fifo is used to synchronize the clock domains between the mac receive clock and the phy?s cl ock (e.g., refclk), used to receive symbols on the local phy?s twisted pair interface. the ieee mode supports up to 1518-byte packet size with the minimum inter-packet gap (ipg). the jumbo packet mode adds latency to the path to support up to 9600-byte packets with the minimum inter-packet gap (ipg). when using jumbo packet mode, a larger ipg is recommended due to the possible compression of the ipg at the output of the fifo.
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 83 of 121 24.26 register 25 (19h) ? interrupt mask register 25.15 ? interrupt pin enable when bit 25.15 is set to ?1?, the hardware interrupt is enabled, meaning that the state of the external interrupt pin (mdint_n) can be influenced by the state of the interrupt status bit (26.15). when bit 25.15 is set to ?0?, the interrupt status bits (re gister 26) continue to be set in response to interrupts, but the interrupt hardware pin mdint_n on the vsc8244 will not be influenced by this particular phy. register 25 (19h) ? interrupt mask register bit name access states reset value sticky 15 interrupt pin enable r/w 1 = enable interrupt pin 0 = disable interrupt pin 0 s 14 speed state-change interrupt mask r/w 1 = enable speed interrupt 0 = disable speed interrupt 0 s 13 link state-change/ energy detect interrupt mask r/w 1 = enable link state/ energy detect interrupt 0 = disable link state/ energy detect interrupt 0 s 12 fdx state-change interrupt mask r/w 1 = enable fdx interrupt 0 = disable fdx interrupt 0 s 11 auto-negotiation error interrupt mask r/w 1 = enable auto-negot iation error interrupt 0 = disable auto-negotiation error interrupt 0 s 10 auto-negotiation-done/ interlock done interrupt mask r/w 1 = enable auto-negotiation-done/ interlock done interrupt 0 = disable auto-negotiation-done/ interlock done interrupt 0 s 9 in-line powered device detected interrupt mask r/w 1 = enable in-line powered device detected inter- rupt 0 = disable in-line powered device detected interrupt 0 s 8 symbol error interrupt mask r/w 1 = enable symbol error interrupt 0 = disable symbol error interrupt 0 s 7 descrambler lock-lost interrupt mask r/w 1 = enable lock-lost interrupt 0 = disable lock-lost interrupt 0 s 6 tx fifo interrupt mask r/w 1 = enable tx fifo interrupt 0 = disable tx fifo interrupt 0 s 5 rx fifo interrupt mask r/w 1 = enable rx fifo interrupt 0 = disable rx fifo interrupt 0 s 4 reserved ro - -- 3 false carrier interrupt mask r/w 1 = enable false carrier interrupt 0 = disable false carrier interrupt 0 s 2 cable impairment detect interrupt mask r/w 1 = enable cable impairment detect interrupt 0 = disable cable impairment detect interrupt 0 s 1 master/slave interrupt mask r/w 1 = enable master/slave interrupt 0 = disable master/slave interrupt 0 s 0 rx_er interrupt r/w 1 = enable rx_er interrupt 0 = disable rx_er interrupt 0 s
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 84 of 121 24.27 register 26 (1ah) ? interrupt status register 26.15 ? interrupt status when bit 26.15 is set to ?1?, an unacknowledged interrupt is pending. the cause of the interrupt can be determined by reading the interrupt status bits in this register. this bit is automatically cleared when read. 26.14 ? speed state-change interrupt status when the operating speed of the phy changes, bit 26.14 is set to "1" if bit 26.14 is set to "1" and if bit 0.12 is also set to "1". this bit is automatically cleared when read. 26.13 ? link state-change/ energy detect interrupt status when the link status of the phy changes, or if actiphy mode is enabled, and energy is detected on the media, bit 26.13 is set to ?1? if bit 25.13 is also set to ?1?. this bit is automatically cleared when read. 26.12 ? fdx state-change interrupt status when the fdx/hdx status of the phy changes, bit 26.12 is set to "1" if bit 26.12 is set to "1" and if bit 0.12 is also set to " 1". this bit is automatically cleared when read. 26.11 ? auto-negotiation error interrupt status when an error is detected by the auto-negotiation state machine, bit 26.11 is set to ?1? if bit 25.11 is also set to ?1?. this bit is automatically cleared when read. register 26 (1ah) ? interrupt status register bit name access states reset value sticky 15 interrupt status ro sc 1 = interrupt pending 0 = no interrupt pending 0 14 speed state-change interrupt sta- tus ro sc 1 = speed interrupt pending 0 13 link state-change/ energy detect interrupt status ro sc 1 = link state-change/ energy detect interrupt pending 0 12 fdx state-change interrupt status 1 ro sc 1 = fdx interrupt pending 0 11 auto-negotiation error interrupt status ro sc 1 = auto-negotiation error interrupt pending 0 10 auto-negotiation-done/ interlock done interrupt status ro sc 1 = auto-negotiation-done/ interlock done inter- rupt pending 0 9 in-line powered device interrupt status ro sc 1 = in-line powered device interrupt pending 0 8 symbol error interrupt status ro sc 1 = symbol error interrupt pending 0 7 descrambler lock-lost interrupt status ro sc 1 = lock-lost interrupt pending 0 6 tx fifo interrupt status ro sc 1 = tx fifo interrupt pending 0 5 rx fifo interrupt status ro sc 1 = rx fifo interrupt pending 0 4 reserved ro - -- 3 false carrier interrupt status ro sc 1 = false carrier interrupt pending 0 2 cable impairment detect interrupt status ro sc 1 = cable impairment detect interrupt pending 0 1 master/slave interrupt status ro sc 1 = master/slave error interrupt pending 0 0 rx_er interrupt status ro 1 = rx_er interrupt pending 0 = no rx_er interrupt pending 0
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 85 of 121 26.10 ? auto-negotiati on-done/interlock do ne interrupt status when the auto-negotiation state machine finishes a negotiation process, bit 26.10 is set to ?1? if bit 25.10 is also set to ?1? . this bit is automatically cleared when read. 26.9 ? in-line powered device interrupt status when a device requiring in-line power over cat-5 is detected, bit 26.9 is set to ?1? if bit 25.9 is also set to ?1?. this bit i s automatically cleared when read. 26.8 ? symbol erro r interrupt status when a symbol error is detected by the descrambler, bit 26.8 is set to ?1? if bit 25.8 is also set to ?1?. this bit is automati cally cleared when read. 26.7 ? descrambler lock-lost interrupt status when the descrambler loses lock, bit 26.7 is set to ?1? if bit 25 .7 is also set to ?1?. this bit is automatically cleared when read. 26.6 ? tx fifo interrupt status when the tx fifo enters an underflow or overflow condition, bi t 26.6 is set to ?1? if bit 25.6 is also set to ?1?. this bit is automatically cleared when read. 26.5 ? rx fifo interrupt status when the rx fifo enters an underflow or over flow condition, bit 26.5 is set to ?1? if bit 25.5 is also set to ?1?. this bit is automatically cleared when read. 26.3 ? false carrier detect interrupt status when the phy has detected a false carrier, bit 26.3 is set to ?1? if bit 25.3 is also set to ?1?. this bit is automatically cle ared when read, 26.2 ? cable impairment detect interrupt status when the phy has detected an impairment on the cat-5 media, bit 26.3 is set to ?1? if bit 25.3 is also set to ?1?. this bit is automatically cleared when read. this feature is dis abled if mii register bits 4:8.5 are all set to "0". 26.1 ? master/slave resolution error interrupt status when a master/slave resolution error is detected, bit 26.1 is set to ?1? if bit 25.1 is also set to ?1?. this bit is automatica lly cleared when read. 26.0 ? rx_er interrupt status when an rx_er condition occurs, bit 26.0 is set to ?1?. this bit is automatically cleared when read.
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 86 of 121 24.28 register 27 (1bh) ? led control register 27.15:6 ? led pin configuration each of the five led pins on each port of the vsc8244 can be co nfigured for one of four functions. these functions are differen t for each led pin. bits 27.15:6 are used to select the function for each led pin. the reset value of these bits is set by the le d configuration bits in the cmode hardware configuration. note: if bits 27.7:6=01, then led1 and led2 become serial outputs. register 27 (1bh) ? led control register bit name access states reset value sticky 15:14 led pin 4 configuration r/w 00 = duplex/collision 01 = activity 10 = link fault 11 = link/activity cmode s 13:12 led pin 3 configuration r/w 00 = collision 01 = duplex/collision 10 = reserved 11 = rx cmode s 11:10 led pin 2 configuration r/w 00 = link10/activity 01 = duplex/collision 10 = link/activity 11 = tx cmode s 9:8 led pin 1 configuration r/w 00 = link100/activity 01 = link10/100/activity 10 = link/activity 11 = link100/1000/activity cmode s 7:6 led pin 0 configuration r/w 00 = link1000/activity 01 = link/activity w/ serial output on led pins 1 and 2 10 = fault 11 = rx cmode s 5 led pulse-stretch rate/ blink rate r/w 1 = 10hz blink rate/ 100ms pulse-stretch 0 = 5hz blink rate/ 200ms pulse-stretch 0 s 4 led pulsing enable r/w 1 = enable 5khz, 20% duty cycle led pulsing for power savings 0 = led pulsing disabled 0 s 3 led pulse-stretch/ blink select r/w 1 = collision, activity, rx and tx functions will pulse-stretch when active. 0 = collision, activity, rx and tx functions will blink when active. cmode s 2 led link/activity behavior r/w 1 = link function indicates link status only 0 = link function will blink or flash when activity is present. blink/flash behavior is selected by pulse-stretch enable and blink/pulse-stretch rate bits. cmode s 1 led link10/100/1000/activity behavior r/w 1 = link10, link 100, link1000, link10/100, and link100/1000 leds indicates link status only 0 = link10, link 100, link1000, link10/100, and link100/1000 leds will blink or flash when activity is present. blink/flash behavior is selected by pulse-stretch enable and blink/ pulse-stretch rate bits. cmode s 0 led duplex/collision behavior r/w 1 = duplex function indicates duplex status only 0 = duplex function will blink or flash when colli- sion is present cmode s
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 87 of 121 24.29 register 28 (1ch) ? auxi liary control & status register 28.15 ? auto-negotiation complete this bit is a copy of bit 1.5, duplicated here for convenience. 28.14 ? auto-negotiation disabled when bit 28.14 is read as a ?1?, this bit indicates that the auto-negotiation process has been disabled. this happens only when register bit 0.12 is set to ?0?. 28.13 ? mdi/mdi-x crossover indication when bit 28.13 returns a ?1?, the auto-negotiation state machine has determined that crossover does not exist in the signal path. the crossover will therefore be performed internally to th e phy, as described by the md i/mdi-x crossover specification. 1 register 28 (1ch) ? auxiliary control & status register bit name access states reset value sticky 15 auto-negotiation complete ro 1 = auto-negotiation complete 0 = auto-negotiation not complete 0 14 auto-negotiation disabled ro 1 = auto-negotiation was disabled 0 = auto-negotiation is enabled 0 13 mdi/mdi-x crosso ver indication ro 1 = mdi/mdi-x crossover detected 0 = mdi/mdi-x crossover not detected 0 12 cd pair swap ro 1 = cd pairs are swapped 0 = cd pairs are not swapped 0 11 a polarity inversion ro 1 = polarity swapped on pair a 0 = polarity not swapped on pair a 0 10 b polarity inversion ro 1 = polarity swapped on pair b 0 = polarity not swapped on pair b 0 9 c polarity inversion ro 1 = polarity swapped on pair c 0 = polarity not swapped on pair c 0 8 d polarity inversion ro 1 = polarity swapped on pair d 0 = polarity not swapped on pair d 0 7 reserved ro - -- 6 actiphy mode enable r/w 1 = enable actiphy power management 0 = disable actiphy power management cmode s 5 fdx status ro 1 = full duplex 0 = half duplex 0 4:3 speed status ro 00 = speed is 10base-t 01 = speed is 100base-tx 10 = speed is 1000base-t 11 = reserved 00 2 reserved ro - -- 1:0 actiphytm sleep timer r/w 00 = 1 second 01 = 2 seconds 10 = 3 seconds 11 = 4 seconds 01 1 this bit is valid only after descr ambler lock has been achieved and as long as bit 18.5 is set to ?0?.
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 88 of 121 28.12 ? cd pair swap 1 when bit 28.12 returns a ?1?, the phy has determined that subchannel cable pairs c and d have been swapped between the far-end transmitted and the receiver. when bit 28.12 returns a ?1?, the phy internally swaps pairs c and d (as long as bit 18.5 is set to ?0?). 1 28.11 ? a polarity inversion when bit 28.11 returns a ?1?, the phy has determined that the polarity of subchannel cable pair a has been inverted between the far-end transmitter and the near-end receiver. when bit 28.11 returns a ?1?, the phy internally corrects the pair inversion . polarity-inversion correction runs in all three modes; as a result, the state of 28.11 is valid only when bit 1.5 is set to ?1? . 28.10 ? b polarity inversion when bit 28.10 returns a ?1?, the phy has determined that the polarity of subchannel cable pair b has been inverted between the far-end transmitter and the near-end receiver. when bit 28.10 returns a ?1?, the phy internally corrects the pair inversion . polarity-inversion correction runs in all three modes; as a result, the state of 28.10 is valid only when bit 1.5 is set to ?1? . 28.9 ? c polarity inversion 2 when bit 28.9 returns a ?1?, the phy has determined that the polarity of subchannel cable pair c has been inverted between the far-end transmitter and the near-end receiver. when bit 28.9 returns a ?1?, the phy internally corrects the pair inversion. polarity-inversion correction runs in all three modes; as a result, the state of 28.9 is valid only when bit 1.5 is set to ?1?. 28.8 ? d polarity inversion 1 when bit 28.8 returns a ?1?, the phy has determined that the polarity of subchannel cable pair d has been inverted between the far-end transmitter and the near-end receiver. when bit 28.8 returns a ?1?, the phy internally corrects the pair inversion. polarity-inversion correction runs in all three modes; as a result, the state of 28.8 is valid only when bit 1.5 is set to ?1?. 28.6 - enable actiphy mode when bit 28.6 is set to a ?1?, the actiphy power management mode is set in the vsc8244. the reset value for this bit is determined by the actiphy bit in the cmode hardware configuration. 28.5 ? fdx status bit 28.5 indicates the actual fdx/hdx operating mode of the phy. 28.4:3 ? speed status bits 27.4:3 indicate the actual operating speed of the phy. 28.1:0 ? actiphy tm and ams sleep timer this sets the time period the phy stays in ?low power? state when actiphy mode (mii register bit 28.6) is enabled before entering into the ?lp wake-up? state. refer to section 19: "actiphy power management" for more information. 1 this bit applies only in 1000base-t mode. 2 this bit applies only in 1000base-t mode.
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 89 of 121 24.30 register 29 (1dh) ? reserved 24.31 register 30 (1eh) - reserved 24.32 register 31 (1fh) ? extended page access 31.0 - extended page access in order to provide additional functionality beyond the ieee802 .3 specified 32 mii registers, the vsc8244 contains an extended register set which supports an additional 15 registers. when bit 31.0 is set to a ?1?, mii registers 16:30 will access the exte nded set of registers. the state of bit 31.0 has no effect on mii registers 0:15. this bit is write only and cannot be read back. register 29 (1dh) ? reserved bit name access states reset value sticky 15:0 reserved ro -- register 30 (1eh) ? reserved bit name access states reset value sticky 15:0 reserved ro - -- register 31 (1fh) ? extended page access bit name access states reset value sticky 15:1 reserved ro - -- 0 extended page access wo 1 = mii registers 16:30 will access extended regis- ter set 0 = mii registers 16:30 will access standard regis- ter set 0
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 90 of 121 24.33 register 16e (10h) - reserved 24.34 register 17e (11h) - clk125 micro clock enable 17e.0 - enable 125mhz micro free-running clock output when this bit is set to ?1?, the vsc8244 provides a free-running, general-purpose clock on the clk125 micro output pin. the electrical specifications for this clock corresponds to the current setting for vddio micro . this clock can be used by a system manager cpu or other control logic. please refer to mii register 20e.8 to set the clk125 micro frequency. by default, this pin is disabled and must be set to a ?1? in order to output a signal. when disabled, this pin is normally driven low. note that only p hy port 0?s bit 17e.0 controls the operation of clk125 micro . 24.35 register 18e (12h) - reserved 24.36 register 19e (13h) - reserved register 16e (10h) ? reserved bit name access states reset value sticky 15:3 reserved ro - -- register 17e (11h) ? clk125 micro clock enable bit name access states reset value sticky 15:1 reserved ro - -- 0 clk125 micro clock output enable r/w 1 = enable clk125 micro output clock pin 0 = disable clk125 micro output clock pin 0 s register 18e (12h) ? reserved bit name access states reset value sticky 15:0 reserved ro - -- register 19e (13h) ? reserved bit name access states reset value sticky 15:0 reserved ro - --
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 91 of 121 24.37 register 20e (14h) - extended phy control register #3 20e.8 - clock frequency mode the freqency of the clk125 micro pin can be changed by using bit 20e.8. this bit is only valid in phy0. 20e.4 - enable link speed auto-downshift when bit 20e.4 is set to a ?1?, the vsc8244 will ?downshift? the autonegotiation ad vertisement to 100base- tx after the number of failed 1000base-t autonegotiation attempts specified in bits 20e.3:2. the reset value of this bit is determined by the link speed downshift bit in the cmode hardware configuration. 20e.3:2 - link speed auto-downshift control bits 20e.3:2 determine the number of unsuccessful 1000base-t autonegotiation attempts that are required before the autonegotiation advertisement is ?downshifted? to 100base- tx. these bits are valid only if bit 20e.4 is set. 20e.1 - link speed auto-downshift status when bit 20e.1 is set to a ?1? and bit 20e.4 is set to a ?1?, the current link speed is the result of a ?downshift? to 100base- tx. when bit 20e.1 is set to a ?1? and bit 20e.4 is cleared, the current link requires a ?downshift? in order to be established. register 20e (14h) ? extende d phy control register #3 bit name access states reset value sticky 15:9 reserved ro - -- 8 clk125 micro frequency r/w 1 = 125mhz clock output on clk125 micro 0 = 4mhz clock output on clk125 micro 0 s 7:5 reserved ro - -- 4 enable link speed auto-downshift r/w 1 = enable auto link speed downshift 0 = disable auto link speed downshift cmode s 3:2 link speed auto-downshift control r/w 00 = downshift after 2 failed attempts 01 = downshift after 3 failed attempts 10 = downshift after 4 failed attempts 11 = downshift after 5 failed attempts 01 s 1 link speed auto-downshift status ro 0 = no downshift 1 = downshift is required or has occurred 0 0 reserved ro - --
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 92 of 121 24.38 register 21e (15h) - eeprom in terface status a nd control register 21e.14 - re-read eeprom on software reset when bit 21e.14 is set to a ?1?, the contents of the eeprom will be re-read and reloaded into the mii registers upon software reset. 21e.13 - eeprom access enable when bit 21e.13 is set to a ?1?, the eeprom address in bits 21 e.10:0 is written to or read from, based on the state of bit 21e.12. the data to read/write resides in register 22e. 21e.12 - eeprom read/write when bit 21e.12 is set to a ?1?, the vsc8244 will read from the eeprom when bit 21e.13 is set. when bit 21e.12 is cleared, the vsc8244 will write to the eeprom when bit 21e.13 is set. 21e.11 - eeprom ready when the vsc8244 is busy reading/writing to the eeprom, bit 21e.11 will be cleared. bit 21e.13 should not be set while bit 21e.11 is cleared. 21e.10:1 - eeprom address these bits contain the eeprom address that the vsc8244 will read from or write to when bit 21e.13 is set. register 21e (15h) - eeprom interf ace status and control register bit name access states reset value sticky 15 reserved ro - -- 14 re-read eeprom on software reset r/w 1 = contents of eeprom should be re-read on software reset 0 = contents of eeprom should not be re-read on software reset 0 ss 13 eeprom access enable r/w sc 1 = execute read or write to eeprom 0 12 eeprom read/write r/w 1 = read from eeprom 0 = write to eeprom 1 11 eeprom ready ro 1 = eeprom is ready for read/write 0 = eeprom is busy 1 10:0 eeprom address r/w eeprom address to read/write 0
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 93 of 121 24.39 register 22e (16h) - eepr om data read/write register 22e.15:18 - eeprom read data after an eeprom read has occurred by setting bits 21e.13 and 21e.12 to a ?1?, the data read from the eeprom is placed in these bits. 22e.7:0 - eeprom write data when an eeprom write is initiate d by setting bits 21e.13 to a ?1? and clearing bit 21e.12, the dat a from these bits is written to the eeprom. 24.40 register 23e (17h) - extended phy control register #4 23e.15:11 - phy address these bits contain the phy address of the current phy port. the reset value of these bits is determined by the phy address bits in the cmode hardware configuration. 23e.10 - enable in-line powered device detection when bit 23e.10 = 1, the vsc8244 will search for devices requir ing cat-5 in-line power as part of the autonegotiation process. 23e.9:8 - in-line powered device detection status bits 23e.9:8 are used by the station manager to determine if a device is connected to the vsc8244 which requires in-line power. these bits are only valid if bit 23e.10 = 1. 23e.7:0 - 1000bt crc counter in 1000bt mode, these bits count the number of packets received that contain a crc error. this counter will saturate at 0ffh and is cleared when read. register 22e (16h) - eeprom data read/write register bit name access states reset value sticky 15:8 eeprom read data ro 8-bit data read from eeprom 0 7:0 eeprom write data r/w 8-bit data to write to eeprom 0 register 23e (17h) - extended phy control register #4 bit name access states reset value sticky 15:11 phy address ro phy address latched on reset cmode 10 enable in-line powered device detection r/w 1 = in-line powered device detection is enabled 0 = in-line powered device detection is disabled 0 s 9:8 in-line powered device detection status ro 00 = searching for devices 01 = device found which requires in-line power 10 = device found which does not require in-line power 11 = reserved 0 7:0 crc counter ro sc crc counter for ethernet packet generator 0
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 94 of 121 24.41 register 24e (18h) ? reserved 24.42 register 25e (19h) ? reserved 24.43 register 26e (1ah) ? reserved 24.44 register 27e (1bh) ? reserved 24.45 register 28e (1ch) ? reserved register 24e (18h) ? reserved bit name access states reset value sticky 15:0 reserved ro - -- register 25e (19h) ? reserved bit name access states reset value sticky 15:0 reserved ro - -- register 26e (1ah) ? reserved bit name access states reset value sticky 15:0 reserved ro - -- register 27e (1bh) ? reserved bit name access states reset value sticky 15:0 reserved ro - -- register 28e (1ch) ? reserved bit name access states reset value sticky 15:0 reserved ro - --
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 95 of 121 24.46 register 29e (1dh) - 1000base-t ethernet packet generator (epg) register #1 29e.15 - epg enable when bit 29e.15 is set to a ?1?, the epg is selected as the driving source for the phy transmit signals, and the mac transmit pins are disabled. when bit 29e.15 is cleared, the mac has full control of the phy transmit signals. 29e.14 - epg run/stop bit 29e.14 controls the beginning and end of packet transmission. when this bit is set to a ?1?, the epg begins the transmissio n of packets. when this bit is cleared, the epg ends the transmission of packets, after the current packet is transmitted. bit 29e.14 is valid only if bit 29e.15 is set to a ?1?. 29e.13 - transmission duration when bit 29e.13 is set to a ?1?, the epg will continuously transmit packets as long as bit 29e.14 is set to a ?1?. if bit 29e.1 3 is cleared, the epg will begin transmission of 30,000,000 packets when bit 29e.14 is set to a ?1?, after which time, bit 29e.14 is automatically cleared. if bit 29e.13 changes during packet tran smission, the new value will not take effect until the epg run/ stop bit (29e.14) has been cleared and set to a ?1? again. 29e.12:11 - packet length bits 29e.12:11 select the length of the packets to be generated by the epg. note that when these bits are set to ?11?, a 10,000 - byte ?jumbo? packet is sent, which may not be compatible with all ethernet equipment. if bits 29e.12:11 change during packet transmission, the new values will not take effect until the epg run/stop bit (29e.14) has been cleared and set to a ?1? again. 29e.10 - inter-packet gap bit 29e.10 selects the inter-packet gap for packets generated by the epg. if bit 29e.10 changes during packet transmission, the new value will not take effect until the epg run/stop bit (29e.14) has been cleared and set to a ?1? again. register 29e (1dh) - 1000base-t ethernet packet generator (epg) register #1 bit name access states reset value sticky 15 epg enable r/w 1 = enable epg 0 = disable epg 0 14 epg run/stop r/w 1 = run epg 0 = stop epg 0 13 transmission duration r/w 1 = continuous 0 = send 30,000,000 packets and stop 0 12:11 packet length r/w 00 = 125 bytes 01 = 64 bytes 10 = 1518 bytes 11 = 10,000 bytes (jumbo packet) 0 10 inter-packet gap r/w 1 = 8,192 ns 0 = 96 ns 0 9:6 destination address r/w msb's lower nibble of the 6-byte destination address 0001 5:2 source address r/w msb's lower nibble of the 6-byte destination addresss 0000 1 reserved ro - -- 0 bad fcs generation r/w 1 = generate packets with bad fcs 0 = generate packets with good fcs 0
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 96 of 121 25 electrical specifications 25.1 absolute maximum ratings stresses listed under absolute maximum ratings may be applied to devices one at a time without causing permanent damage. functionality at or above the values listed is not implied. ex posure to these values for extended periods may affect device reliability. symbol min max unit parameter description & conditions p d 3.4 w worst case power dissipation. t storage -65 150 c storage temperature range. t j +125 c absolute maximum junction temperature. v dd(analog) -0.5 4.0 v dc voltage on analog i/o supply pin. v dd(io) -0.5 4.0 v dc voltage on any digital i/o supply pin. v dd(5v) -0.5 5.5 v dc voltage on any 5v-tolerant digital input pin. v dd(dig-core) -0.5 1.5 v dc voltage on any digital core supply pin. v dd(analog-core) -0.5 1.5 v dc voltage on any analog core supply pin. v pin(dc) -0.5 v dd + 0.5 v dc voltage on any non-supply pin. v esd(hbm) 2kv esd voltage on any pin, per event, according to the human body model. cesd 2 kv cable-sourced esd tolerance, per event, at 200 meters. i latchup -200 +200 ma t = +85c, valid for all i/o signal pins. electrostatic discharge this device can be damaged by esd. vitesse recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures may adversely affect reliability of the device.
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 97 of 121 25.2 recommended operating conditions symbol min typ max unit parameter description & conditions vdd33 3.0 3.3 3.6 v dc voltage on vdd33 pins vddio mac 3.0 2.3 1.4 3.3 2.5 1.5 3.6 2.7 1.6 v dc voltage on vddio mac pins 1 1 on-chip i/o calibration only valid within these recommended operating conditions. v ref (hstl) .68 .75 .90 v hstl i/o reference voltage vddio micro 3.0 2.3 1.4 3.3 2.5 1.5 3.6 2.7 1.6 v dc voltage on vddio micro pins 1 vddio ctl 3.0 2.3 3.3 2.5 3.6 2.7 v dc voltage on vddio ctl pins 1 vdd12 1.14 1.2 1.26 v dc voltage on vdd12 pins vdddig 1.14 1.2 1.26 v digital core logic dc power supply voltage. f refclk 25 125 mhz local reference clock (refclk) nominal frequency. refer to f tol for min and max values. f tol (refclk) -100 +100 ppm reference clock frequency offs et tolerance over speci- fied temperature range (25mhz or 125mhz) 2 2 refer to the applications note using jumbo packets with simpliphys for further information about clocking and frequency offset tolerance specifications when jumbo packet suppor t is required. f tol (link) -1500 +1500 ppm link partner frequency offset tolerance (for any link speed) 2 r ext 2.00 k external reference circuit bi as resistor (1% tolerance). c ref_filt 1.0 f external reference generator filter capacitor (10% tol- erance). t (oper) 0100c lower limit of specificatio n is ambient temperature, and upper limit is case temperature.
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 98 of 121 25.3 thermal application data 25.4 package thermal specifications - 260 hs-pbga printed circuit board conditions (jedec jesd51-9) pcb layers 64 pcb dimensions (mm x mm) 101.6 x 114.3 101.6 x 114.3 pcb thickness (mm) 1.6 1.6 environment conditions maximum operation junction temperature (oc) 125 125 ambient free-air operating temperature (oc) 70 70 worst case power dissipation (w) 3.4 3.4 table 39. thermal air flow specifi cations - 260 ball hsbga 19mm package symbol min typ max unit parameter description & conditions ja (0 m/s air- flow) 17.5 20.2 c/w junction-to-ambient thermal resistance 6-layer 4-layer ja (1 m/s air- flow) 14.8 17.5 c/w junction-to-ambient thermal resistance 6-layer 4-layer ja (2 m/s air- flow) 13.8 16.2 c/w junction-to-ambient thermal resistance 6-layer 4-layer table 40. thermal specifications - 260 ball hsbga 19mm package symbol min typ max unit parameter description & conditions t a 70 c ambient free-air operating temperature t j 125 c maximum operating junction temperature jc 5.1 5.2 c/w junction-to-case thermal resistance 6-layer 4-layer jt 4.47 4.61 c/w junction-to-top center of case thermal resistance 6-layer 4-layer jb 10.4 12.2 c/w junction-to-board thermal resistance 6-layer 4-layer
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 99 of 121 25.5 current and power consumption estimates typical power supply current and power consumption information is provided below for pcb design targets. all typical data below is based on engineering measurements at nominal vo ltages with 1000base-t rgmii, 64-byte random data pattern under 100% utilization in full-duplex mode. a maximum margin of 20% should be included to account for variation in the specified power supply voltage ranges, as well as for variati on due to the normal silicon process spread and temperature conditions. table 41. current and power consumption estimates - hstl @ 1.5v, rgmii mode, no leds, no clk125 symbol min typ max unit description i vdd33 397 ma analog 3.3v power supply current into vdd33 pins i vddiomac 50 ma digital i/o supply current into vddio mac @ 1.5v i vddiomicro 0.3 ma digital i/o supply current into vddio micro @ 3.3v i vddioctl 2.5 ma digital i/o supply current into vddio ctl @ 3.3v i vdd12 136 ma analog 1.2v power supply current into vdd12 pins i vdddig 821 ma digital 1.2v core power supply current into vdddig pins p d 636 mw power dissipation per port (no leds) table 42. current and power consumption esti mates - 2.5v, rgmii mode, no leds, no clk125 symbol min typ max unit description i vdd33 397 ma analog 3.3v power supply current into vdd33 pins i vddiomac 98.6 ma digital i/o supply current into vddio mac @ 2.5v i vddiomicro 0.3 ma digital i/o supply current into vddio micro @ 3.3v i vddioctl 2.5 ma digital i/o supply current into vddio ctl @ 3.3v i vdd12 136 ma analog 1.2v power supply current into vdd12 pins i vdddig 821 ma digital 1.2v core power supply current into vdddig pins p d 679 mw power dissipation per port (no leds) table 43. current and power consumption esti mates - 3.3v, rgmii mode, no leds, no clk125 symbol min typ max unit description i vdd33 397 ma analog 3.3v power supply current into vdd33 pins i vddiomac 149 ma digital i/o supply current into vddio mac @ 3.3v i vddiomicro 0.3 ma digital i/o supply current into vddio micro @ 3.3v i vddioctl 2.5 ma digital i/o supply current into vddio ctl @ 3.3v i vdd12 136 ma analog 1.2v power supply current into vdd12 pins i vdddig 821 ma digital 1.2v core power supply current into vdddig pins p d 740 mw power dissipation per port (no leds)
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 100 of 121 25.6 dc specifications 25.6.1 digital pins referenced to vddio = 3.3v the specifications listed in table 44 and ta b l e 4 5 are valid only when t ambient = 25c, vddio = 3.3v, vdddig = 1.2v, vdd33 = 3.3v, vssio = 0v, and vsss = 0v. 25.6.2 digital pins referenced to vddio = 2.5v table 44. digital pins sp ecifications (vddio = 3.3v) symbol min typ max unit parameter description & conditions v oh 2.1 vddio + 0.3 v output high voltage. vddio = min, i oh = -1.5ma v ol gnd 0.5 v output low voltage. vddio = min, i ol = 1.5ma v ih 2.0 v input high voltage. v il 0.9 v input low voltage. i ileak -10 10 a input leakage current. i oleak -10 10 a output leakage current. i ol 12 ma output low current drive strength i oh -12 ma output high current drive strength z o 50 output driver impedance table 45. digital pins sp ecifications (vddio = 2.5v) symbol min typ max unit parameter description & conditions v oh 2.0 vddio + 0.3 v output high voltage. vddio = min, i oh = -1.0ma v ol gnd - 0.3 0.4 v output low voltage. vddio = min, i ol = 1.0ma v ih 1.7 v input high voltage. vddio = min v il 0.7 v input low voltage. vddio = min i ileak -10 10 a input leakage current. i oleak -10 10 a output leakage current. i ol 12 ma output low current drive strength i oh -12 ma output high current drive strength z o 50 output driver impedance
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 101 of 121 25.6.3 digital pins (vddio = 1.5v hstl) the following specifications are valid only when t ambient = 25c, vddio = 1.5v, vdddig = 1.2v, vdd33 = 3.3v, vssio = 0v, and vsss = 0v. table 46. digital pins sp ecifications (vddio = 1.5v) symbol min typ max unit parameter description & conditions v oh vddio - 0.4 v output high voltage vddio = min, i oh = -1.0ma v ol 0.4 v output low voltage vddio = min, i ol = 1.0ma v ih vref + 0.12 vddio + 0.3 v input high voltage vddio = min v il - 0.3 vref - 0.12 v input low voltage vddio = min i ileak 10 a input leakage current i oleak 10 a output leakage current i ol 12 ma output low current drive strength i oh -12 ma output high current drive strength z o 50 output driver impedance
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 102 of 121 25.6.4 led output pins (led[4:0]_n) the following specifications are valid over a volta ge range of 2.3v to 1.3v applied to the led pins. 25.7 clocking specifications 25.7.1 reference clock option the following component specifications should be used to select a clock reference for use with the vsc8244 1 . table 47. led output pins specifications symbol min typ max unit parameter description & conditions i ileak 10 a input leakage current i oleak 10 a output leakage current i ol 18 ma output low current drive strength i oh -18 ma output high current drive strength z o 50 output driver impedance table 48. reference clock option specifications symbol min typ max unit parameter description & conditions f tol-25mhz -100 ppm 25 +100 ppm mhz total frequency offset tolerance (25mhz clock option), including, initial offset, stability over temperature. t r1, t f1 4ns rise and fall time (20% to 80%), 25mhz clock option. t r2, t f2 0.8 ns rise and fall time (20% to 80%), 125mhz clock option. duty 45 55 % duty cycle (25mhz a nd 125mhz clock options). 1 refer to the applications note using jumbo packets with simpliphys for further information about clocking and fr equency offset toleranc e specifications when jumbo packet support is required.
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 103 of 121 25.7.2 crystal option the following component specifications should be used to select a crystal for use with the vsc8244 1 . refer to the application note using jumbo packets with simpliphys for further information about clocking and frequency offset tolerance specifications when jumbo packet support is required. 25.8 system timing specifications 25.8.1 rgmii mode timing for rgmii mode, the following specifications are valid when the i/o power supply (vddio mac ) is 1.5v, 2.5v, or 3.3v, 5%, per the rgmii v2.0 specification, and the mac i/f selection bits have been set to rgmii mode. see mii register bit 23.11:8 and the rgmii specification for more information. table 49. crystal option specifications symbol min typ max unit parameter description & conditions f ref 25 mhz fundamental mode, at-cut type, parallel resonant crystal reference frequency. f tol(total) -50 +50 ppm fundamental mode, at-cut type, parallel resonant crystal total frequency offset, including, initial offset, stability over temperature, aging and capacitive load- ing c l 18 20 pf crystal parallel load capacitance. c l-ext 33 pf crystal external load capacitors (c1 and c2) to gnd 1 1 these values can depend on board parasitics. esr 10 30 equivalent series resistance of crystal. p d 0.5 mw crystal oscillator drive level. table 50. rgmii mode ac timing specifications symbol min typ max unit parameter description & conditions t skew t -500 0 500 ps data to clock output skew (at phy) ? uncompensated mode. t skew r 11.82.6ns data to clock output skew (at receiver) ? uncompensated mode. 1 t setup t 1.2 2.0 0 ns data to clock output setup (at phy integrated delay) 2 t hold t 1.2 2.0 0 ns data to clock output setup (at transmitter integrated delay) 2 t setup r 1.0 2.0 0 ns data to clock output setup (at receiver integrated delay) 2 t hold r 1.0 2.0 0 ns data to clock output setup (at phy integrated delay) 2 t cyc1000 t cyc100 t cyc10 7.2 36 360 8 40 400 8.8 44 440 ns clock cycle duration. duty 1000 45 50 55 % duty cycle for 1000base-t. 3 duty 10/100 40 50 60 % duty cycle for 10base-t and 100base-tx. 3 t r, t f .75 ns rise, fall time (20% to 80%).
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 104 of 121 figure 27 diagrams rgmii timing and multiplexing in uncompensated mode. the rgmii specification (v2.0) defines the following relationship between the clock and data signals at the mac/phy interface: to meet this timing specification, a 1.5ns delay to the tx_clk_n and rx_clk_n signals is typically added on the pc board using a long ?trombone shaped? trace. the vsc8244 also includes an optional mode of operation where the pcb delay is handled internally (on-chip). this operating mode can be enabled by setting mii register 23.11:8 high. in this operation mode, the vsc8244 expects the following relationship between tx_clk_n and td on the transmit side and rx_clk_n and rd on the receive side: v thresh1.5 v thresh2.5 v thresh3.3 0.75 1.25 1.65 v v v tx_clk_n switching threshold based on vdd mac 1 this implies that pc board design will require clocks to be routed such that an additional trace delay of greater than 1.5ns an d less than 2.0ns will be added to the associated clock signal. this is normal operating mode (rgmii timi ng is not compensated). to enable rgmii timing compensation, see mii register 23.11:8 . 2 rgmii-id mode (rgmii with i nternal d elay compensation on) - a 2ns delay is added to the tx_clk_n and rx_clk_n signals inside the phy. 3 duty cycle may be stretched or shrunk during speed changes or wh ile transitioning to a received packet?s clock domain, as long as the minimum duty cycle is not violated, and stretching occurs for no more than three t cyc of the lowest speed transitioned between. table 50. rgmii mode ac timing specifications (continued) symbol min typ max unit parameter description & conditions t skew t txd[3:0] tx_ctl tx_clk (at transmitter) tx_clk (at receiver) t skew r txd[3:0] txd[7:4] txen txerr t skew t rxd[3:0] rx_ctl rx_clk (at transmitter) rx_clk (at receiver) t skew r rxd[3:0] rxd[7:4] rxen rxerr t cyc 80% 20% t r , t f v thresh figure 27. rgmii uncompensated ac timing and multiplexing
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 105 of 121 since no ?trombone shaped? traces are requir ed with this approach, the advantages of this compensated timing of rgmii v2.0 include: ? simplified board design ? more compact routes; less board area ? lower emi emissions ? greater distance possible between the mac and phy ? improved signal integrity for a given distance between the mac and phy. t setup t txd[3:0] tx_ctl tx_clk (at transmitter) tx_clk (at receiver) t setup r txd[3:0] txd[7:4] txen txerr rxd[3:0] rx_ctl rx_clk (at transmitter) rx_clk (at receiver) rxd[3:0] rxd[7:4] rxen rxerr tx_clk with internal delay added t hold r t hold t t setup t rx_clk with internal delay added t hold r t hold t delay = 2.0ns delay = 2.0ns v thresh figure 28. rgmii compensated ac timing and multiplexing
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 106 of 121 25.8.2 rtbi mode timing for rtbi mode, the following specifications are valid when the i/o power supply (vddio mac ) is 1.5v, 2.5v, or 3.3v, 5%, per the rgmii (v2.0) specification, and the mac i/fselection bits have been set to rtbi mode. see mii register bit 23.11:8 and the rtbi specification for more information. table 51. rtbi mode ac timing specifications symbol min typ max unit parameter description & conditions t skew t -500 0 500 ps data to clock output skew (at phy) ? uncompensated mode. t skew r 11.82.6ns data to clock output skew (at receiver) ? uncompensated mode. 1 1 this implies that pc board design will require clocks to be routed such that an additional trace delay of greater than 1.5ns an d less than 2.0ns will be added to the associated clock signal. this is normal operating mode (rtbi timing is not compensated). to enable rgmii timing compensation, s ee mii register 23.11:8 . t setup t 1.2 2.0 0 ns data to clock output setup (at phy integrated delay) 2 2 rtbi compensated mode (rgmii with i nternal d elay compensation on) - a 2ns delay is added to the tx_clk_n and rx_clk_n signals inside the phy. t hold t 1.2 2.0 0 ns data to clock output setup (at transmitter integrated delay) 2 t setup r 1.0 2.0 0 ns data to clock output setup (at receiver integrated delay) 2 t hold r 1.0 2.0 0 ns data to clock output setup (at phy integrated delay) 2 t cyc1000 t cyc100 t cyc10 7.2 36 360 8 40 400 8.8 44 440 ns clock cycle duration. duty 1000 45 50 55 % duty cycle for 1000base-t. 3 3 duty cycle may be stretched or shrunk during speed changes or wh ile transitioning to a received packet?s clock domain, as long as the minimum duty cycle is not violated, and stretching occurs for no more than three t cyc of the lowest speed transitioned between. duty 10/100 40 50 60 % duty cycle for 10base-t and 100base-tx. 3 t r, t f .75 ns rise, fall time (20% to 80%). v thresh1.5 v thresh2.5 v thresh3.3 0.75 1.25 1.65 v v v tx_clk_n voltage threshold based on vddio mac
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 107 of 121 figure 29 diagrams rtbi timing and multiplexing in uncompensated mode. the rgmii specification (v2.0) defines the following relationship between the clock and data signals at the mac/phy interface: to meet this timing specification, a 1.5ns delay to the tx_clk_n and rx_clk_n signals is typically added on the pc board using a long ?trombone shaped? trace. the vsc8244 also includes a mode of operation where the additi on of this delay is handled internally. this operating mode can be enabled by setting mii register 23.11:8 high. in this operation mode, the vsc8244 expects the following relationship between tx_clk_n and td on the transmit side and rx_clk_n and rd on the receive side: t skew t txd[3:0] tx_ctl tx_clk (at transmitter) tx_clk (at receiver) t skew r txd[3:0] txd[8:5] txd[4] txd[9] t skew t rxd[3:0] rx_ctl rx_clk (at transmitter) rx_clk (at receiver) t skew r rxd[3:0] rxd[8:5] rxd[4] rxd[9] t cyc 80% 20% t r , t f v thresh figure 29. rtbi uncompensated ac timing and multiplexing
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 108 of 121 since no ?trombone shaped? trace is required with this approac h, the advantages of this compensated timing over rgmii v2.0 include: ? simplified board design ? more compact routes; less board area ? lower emi emissions ? greater distance possible between the mac and phy ? improved signal integrity for a given distance between the mac and phy. t setup t txd[3:0] tx_ctl tx_clk (at transmitter) tx_clk (at receiver) t setup r txd[3:0] txd[8:5] txd[4] txd[9] rxd[3:0] rx_ctl rx_clk (at transmitter) rx_clk (at receiver) rxd[3:0] rxd[8:5] rxd[4] rxd[9] tx_clk with internal delay added t hold r t hold t t setup t rx_clk with internal delay added t hold r t hold t delay = 2.0ns delay = 2.0ns v thresh figure 30. rtbi compensated ac timing and multiplexing
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 109 of 121 25.8.3 jtag timing the following specifications are valid only when the i/o power supply (vddio ctl ) is at either 3.3v, 5%, or 2.5v, 5%. figure 31. jtag interface ac timing table 52. jtag interface ac timing specifications symbol min typ max unit parameter description & conditions t tck-period 100 ns tck period. t tck-high 45 ns tck minimum pulse width high. t tck-low 45 ns tck minimum pulse width low. t tdi/tms-setup 10 ns (tms or tdi) to tck setup time. t tdi/tms-hold 10 ns (tms or tdi) to tck hold time. t tdo-delay 15 ns tdo delay from tck. tck tdi tms t tdi/tms-setup t tdi/tms-hold t tck-period t tck-high t tck-low t tdo-delay tdo
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 110 of 121 25.8.4 smi timing the following specifications are valid only when the i/o power supply (vddio micro ) is at either 3.3v, 5%, or 2.5v, 5%. note: at 16mhz, a 400 ? pull-up resistor on the mdio pin is recommended; otherwise, a 2k ? pull-up resistor is recommended at 2mhz. figure 32. smi ac timing table 53. smi ac timing specifications symbol min typ max unit parameter description & conditions f mdc 0 2.5 12.5 mhz mdc clock frequency. t mdc-high 20 50 ns mdc clock pulse width high. t mdc-low 20 50 ns mdc clock pulse width low. t mdio-setup 10 ns mdio to mdc setup time when sourced by station manager. t mdio-hold 10 ns mdio to mdc hold time when sourced by station manager. t r ,t f 100 t mdc x 10% 1 1 for f mdc above 1mhz, the minimum rise and fall times are in relation to the frequency of the mdc clock period. example: if f mdc = 2mhz, then the minimum t r / t f is 50ns. ns mdc rise and fall time. for mdc = 0 - 1mhz for mdc = 1mhz - f mdc (max) t mdio-delay 10 300 ns mdc to mdio delay time from vsc8244. delay will depend on value of external pull-up resistor on mdio pin. mdc t mdio-setup data mdc t mdio-hold t mdc-high t mdc-low t mdio-delay data f mdc mdio (input) mdio (output)
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 111 of 121 25.8.5 mdint timing the following specifications are valid only when the i/o power supply (vddio micro ) is at either 3.3v, 5%, or 2.5v, 5%. 25.8.6 serial led_clk and led_data timing the following specifications are valid only when the i/o pow er supply (vdd33) is at either 3.3v, 5%, or 2.5v, 5%. figure 33. led_clk and led_data output ac timing table 54. mdint ac timing specifications symbol min typ max unit parameter description & conditions t f 110 ns mdint fall time, assuming a 2.2k ? external pull-up resistor and a 50pf total capacitive load. table 55. led_clk and led_data output ac timing specification symbol min typ max unit parameter description & conditions t led_clk 1 s led_clk output period. t led_clk-pause 25 ms led_clk pause between led bit sequence repeat (un-preambled mode). t led_data-delay 15 ns led_data propagation delay from rising edge of led_clk. led_clk led_data t led_data-delay t led_clk t led_clk-pause bit 1 of 44 bit 44 of 44 ....................... bit 1 of 44
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 112 of 121 25.8.7 refclk timing the following specifications are valid only when the i/o power supply (vdd33) is at either 3.3v, 5%, or 2.5v, 5%. refer to the application note using jumbo packets with simpliphys for further information about clocking and frequency offset tolerance specifications when jumbo packet support is required. figure 34. refclk ac timing table 56. refclk ac timing specifications symbol min typ max unit parameter description & conditions t refclk25 40 ns reference clock period, pllmode = 0 (25mhz reference). t refclk125 8ns reference clock period, pllmode = 1 (125mhz reference). f stability 50 ppm reference clock frequency stability (0c to 70c). t duty 40 50 60 % refclk duty cycle in both 25mhz and 125mhz modes. j refclk25, j refclk125 300 ps total jitter of 25mhz or 12 5mhz reference clock (peak- to-peak). t r/f (refclk25) 4ns reference clock rise time, 25mhz mode (20% to 80%). t r/f (refclk125) 1ns reference clock rise time, 125mhz mode (20% to 80%). refclk 80% 20% t r , t f t refclk t duty
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 113 of 121 25.8.8 clk125 mac and clk125 micro timing the following specifications are valid only when the i/o power supply (vddio mac for clk125 mac ) is at either 3.3v 5%, 2.5v 5%, or 1.5v 5%. the following specifications are valid only when the i/o power supply (vddio micro for clk125 micro ) is at either 3.3v 5%, or 2.5v 5%. figure 35. clk125 ac timing table 57. clk125 ac timing specifications symbol min typ max unit parameter description & conditions t clk125mac 8 ns reference clock period. t clk125micro 250 8 ns reference clock period. either 4mhz, or 125mhz f stability 50 ppm reference clock frequency stability (0c to 70c). t duty 40 50 60 % reference clock duty cycle. j clk125 300 ps total jitter of reference clock (peak-to-peak). t r/f (clk125) 1 ns reference clock rise time (20% to 80%). clk125 80% 20% t r , t f t clk125 t duty clk125 micro 80% 20% t r , t f t clk125micro t duty
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 114 of 121 25.8.9 reset timing the following specifications are valid only when the i/o power supply (vddiomicro) is at either 3.3 v, 5%, or 2.5 v, 5%. figure 36. reset ac timing table 58. reset ac timing specification symbol min typ max unit description conditions t reset 100 ns reset assertion time t ready 13 20 ms reset to smi active time reset t reset refclk t ready mdc
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 115 of 121 26 packaging specifications 26.1 19mm hs-pbga mech anical specification figure 37. 19mm hs-pbga mechanical specification 26.2 package moisture sensitivity moisture sensitivity level ratings for vitesse products comply with the joint ipc and jedec standard ipc/jedec j-std-020. vsc8244hg is rated moisture sensitivity level 3 or better. vsc8244xhg is rated moisture sensitivity level 4. for more information, see the ipc and jedec standard.
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 116 of 121 27 ordering information lea d(pb )-free products from vitesse comply with the temperat ures and profiles defined in the joint ipc and jedec standard ipc/jedec j-std-020. for more information, see the ipc and jedec standard. 27.1 devices 27.2 related devices part number package type description vsc8244hg 260 hs-pbga 1mm ball pitch 19x19mm body quad 10/100/1000base-t phy with rgmii and rtbi interfaces vsc8244xhg 260 hs-pbga 1mm ball pitch 19x19mm body lead(pb)-free, quad 10/1 00/1000base-t phy with rgmii and rtbi interfaces part number package type description vsc8224hg 260 hs-pbga 1mm ball pitch 19x19mm body quad 10/100/1 000base-t and 1000base-x phy with rgmii/rtbi interfaces vsc8224xhg 260 hs-pbga 1mm ball pitch 19x19mm body lead(pb)-free, quad 10/100/1000base-t and 1000base-x phy with rg mii/rtbi interfaces vsc8234hg 260 hs-pbga 1mm ball pitch 19x19mm body quad 10/100/1000base-t phy with sgmii/1000base-x serdes mac interfaces vsc8234xhg 260 hs-pbga 1mm ball pitch 19x19mm body lead(pb)-free, quad 10/100/1000base-t phy with sgmii/1000base-x serdes mac interfaces
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 117 of 121 28 design guidelines the complete set of support documentation for the vsc8244, including a text file that can be used as the startup script, is available on the vitesse web site, https://www.vitesse.com . access to some documents may require the filing of a non- disclosure agreement. 28.1 required smi register write sequence at initialization, a number of internal registers must be changed from their default values. a series of register writes must be executed after each devic e power-up or reset. a microcontroller or a startup configuration eeprom (connected to th e device as described in section 22.4.2, ?programming multiple vsc8244 using the same eeprom,? on page 56, must be incl uded in the system design). the register rewrites are listed in section 22.4: "eeprom interface" . in executing the writes, use the format: smiwrite[phy, register, data]. all register and data values listed in the table are in hexadecimal notation. 28.2 interoperability wi th intel 82547e1 l322sq96 the intel 82547e1 phy, by design, links in slave mode with over 99% probability and then changes its operating mode to a non- ieee-compliant manner shortly after responding to a master link partner?s initial transm ission. the timing of this event is suc h that, over cabling shorter than approximately 2 meters in length , the affected link partner drops the link and attempts to link again. this cycle can re peat indefinitely. table 59. startup write sequence changes phy register data phy register data smiwrite 0 1f 2a30 smiwrite 2 1f 2a30 smiwrite 0 08 0212 smiwrite 2 08 0212 smiwrite 0 1f 52b5 smiwrite 2 1f 52b5 smiwrite 0 10 afa4 smiwrite 2 10 afa4 smiwrite 0 12 000f smiwrite 2 12 000f smiwrite 0 11 492a smiwrite 2 11 492a smiwrite 0 10 8fa4 smiwrite 2 10 8fa4 smiwrite 0 1f 2a30 smiwrite 2 1f 2a30 smiwrite 0 08 0012 smiwrite 2 08 0012 smiwrite 1 1f 2a30 smiwrite 3 1f 2a30 smiwrite 1 08 0212 smiwrite 3 08 0212 smiwrite 1 1f 52b5 smiwrite 3 1f 52b5 smiwrite 1 10 afa4 smiwrite 3 10 afa4 smiwrite 1 12 000f smiwrite 3 12 000f smiwrite 1 11 492a smiwrite 3 11 492a smiwrite 1 10 8fa4 smiwrite 3 10 8fa4 smiwrite 1 1f 2a30 smiwrite 3 1f 2a30 smiwrite 1 08 0012 smiwrite 3 08 0012
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 118 of 121 a series of register writes must be executed after each devic e power-up or reset. a microcontroller or a startup configuration eeprom (connected to th e device as described in section 22.4.2, ?programming multiple vsc8244 using the same eeprom,? on page 56, must be incl uded in the system design). the register rewrites are listed in section 22.4: "eeprom interface" . in executing the writes, use the format: smiwrite[phy, register, data]. all register and data values listed in the table are in hexadecimal notation. table 60. startup write sequence changes for intel 82547e1 interoperability phy register data phy register data smiwrite 0 1f 2a30 smiwrite 2 1f 2a30 smiwrite 0 08 0212 smiwrite 2 08 0212 smiwrite 0 1f 52b5 smiwrite 2 1f 52b5 smiwrite 0 12 0004 smiwrite 2 12 0004 smiwrite 0 11 0671 smiwrite 2 11 0671 smiwrite 0 10 8fae smiwrite 2 10 8fae smiwrite 0 1f 2a30 smiwrite 2 1f 2a30 smiwrite 0 08 0012 smiwrite 2 08 0012 smiwrite 0 1f 0000 smiwrite 2 1f 0000 smiwrite 0 12 0049 smiwrite 2 12 0049 smiwrite 1 1f 2a30 smiwrite 3 1f 2a30 smiwrite 1 08 0212 smiwrite 3 08 0212 smiwrite 1 1f 52b5 smiwrite 3 1f 52b5 smiwrite 1 12 0004 smiwrite 3 12 0004 smiwrite 1 11 0671 smiwrite 3 11 0671 smiwrite 1 10 8fae smiwrite 3 10 8fae smiwrite 1 1f 2a30 smiwrite 3 1f 2a30 smiwrite 1 08 0012 smiwrite 3 08 0012 smiwrite 1 1f 0000 smiwrite 3 1f 0000 smiwrite 1 12 0049 smiwrite 3 12 0049
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 119 of 121 29 product support all support documents for the vsc8244 can be accessed on the sitestation website at http://design.vitesse.com. access to some documents may require the filing of non-disclosure agreement with vitesse. 29.1 available documents and application notes ? startup script file (at initialization, a number of internal registers must be changed from their default values. see vsc8244 rev c startup script text file). ? ibis model ? orcad symbol ? bsdl file ? package pinout excel spreadsheet file ? design & layout guidelines - applications note ? simpliphy'd magnetics for emi control - applications note ? using jumbo packets with simpliphys - application note ? unh test report additional applications notes and information about reference designs using the vsc8244 phy device can be accessed at the vitesse web site.
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 120 of 121 121 30 document history & notices table 61. document revision history revision number date comments 0.2.0 apr 12 04 ? veriphy functional changes. removed re isters 24e-28e. this feature requires support from an external mcu/cp u and the veriphy software library. contact vitesse semiconductor for more information. ? added undocumented pins: c8, m15, r16 to the pin descriptions. updated jtag, reset , soft_reset , tx_clk_n, eedat, eeclk pin descriptions. ? added section 11.5, 11.6, 12.5, 16, 31.1, 32.3 ? updated sections 12.3, 12.4, 13, 15, 19, 21, 22, 23.3, 23.4, 24, 25, 26, 26.2, 28.5, 29, 35 ? simplified register 0-15 descriptions. clause 37 resiters view was removed from the datasheet to avoid confusion as 10 00base-x is not supported in this device. ? updated register 16-18, 22-24, 28-30, 16e, 22e 2.0 june 7 04 ? updated document style to reflect vitesse corporate standards. ? added design guidelines section. 2.1 aug 4 04 ? removed references to 216 ep-lqfp package option. 4.0 sep 30 04 ? changed figures 2 and 19. ? removed sections 10.1 and 10.2, including figures 7 and 8. ? updated sections 13, 14, 15, 17, 17.1, 19.3, 21.1, 23.1, 24.2, 24.4, 24.5, 24.6, 24.32, 25.2, 25.5, 25.6.1, 25.6.2, 25.6.3, 25.7.1, 25.7.2, 29.1. ? added sections 25.8.9 and 26.2. 4.1 june 2006 ? added ordering information for lead(pb)-free products. for more information, see section 27: "ordering information" . also, for the msl rating of the lead(pb)-free products, see section 26.2: "package moisture sensitivity" .
vsc8244 data sheet vmds-10108 revision 4.1 june 2006 121 of 121 121 c opyright ? 2004, 2006 by vitesse semiconductor corporation printed in the u.s.a v itesse semiconductor corporation (?vitesse?) retains the right to make changes to its products or specifications to improve per formance, reliability or manufacturability. all infor - mation in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. whil e t he information furnished herein is held to be accurate and reliable, no responsibility will be assumed by vitesse for its use. furthermore, the information contained herein doe s not convey to the purchaser of microelectronic devices any license under the patent right of any manufacturer. v itesse products are not intended for use in life support products where failure of a vitesse product could reasonably be expect ed to result in death or personal injury. anyon e using a vitesse product in such an application without express written consent of an officer of vitesse does so at their own ri sk, and agrees to fully indemnify vitesse for any dam - a ges that may result from such use or sale. v itesse semiconductor corporation is a registered trademark. all other products or service names used in this publication are fo r identification purposes only, and may be trade - marks or registered trademarks of their respective companies. all other trademarks or registered trademarks mentioned herein ar e the property of their respective holders. corporate headquarters vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: 1-800-vitesse fax:1-(805) 987-5896 for application support, latest technical li terature, and locations of sales offices, please visit our web site at www.vitesse.com

▲Up To Search▲

Price & Availability of VITESSESEMICONDUCTORCORP-VSC8244XHG

	To Download VITESSESEMICONDUCTORCORP-VSC8244XHG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .